Si4133G
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)
Parameter1
Symbol Test Condition
Min Typ Max Unit
XIN Input Frequency
Reference Amplifier Sensitivity
fREF
VREF
—
13
—
MHz
0.5
—
VDD
VPP
+0.3
Phase Detector Update Frequency
RF1 Center Frequency Range
fφ
fCEN
fφ = fREF/R
200
KHz
947
—
1720 MHz
RF2 Center Frequency Range
IF VCO Center Frequency
Tuning Range from fCEN
RF1 VCO Pushing
fCEN
789
—
1429 MHz
fCEN
526
—
952
MHz
Note: LEXT ±10%
–5
—
5
%
Open loop
—
0.5
— MHz/V
RF2 VCO Pushing
—
0.4
— MHz/V
IF VCO Pushing
—
0.3
— MHz/V
RF1 VCO Pulling
RF2 VCO Pulling
IF VCO Pulling
RF1 Phase Noise
VSWR = 2:1, all
phases, open loop
1 MHz offset
—
0.4
—
MHzPP
—
0.1
—
MHzPP
—
0.1
—
MHzPP
—
–132
— dBc/Hz
3 MHz offset
—
–142
— dBc/Hz
RF1 Integrated Phase Error
100 Hz to 100 kHz
—
0.9
— deg rms
RF2 Phase Noise
1 MHz offset
—
–134
— dBc/Hz
3 MHz offset
—
–144
— dBc/Hz
RF2 Integrated Phase Error
100 Hz to 100 kHz
—
0.7
— deg rms
IF Phase Noise
100 kHz offset
—
–117
— dBc/Hz
IF Integrated Phase Error
100 Hz to 100 kHz
—
0.4
— deg rms
RF1 Harmonic Suppression
Second Harmonic
—
–26
—
dBc
RF2 Harmonic Suppression
—
–26
—
dBc
IF Harmonic Suppression
—
–26
—
dBc
RFOUT Power Level
IFOUT Power Level
RF1 Reference Spurs
ZL = 50 Ω
ZL = 50 Ω
Offset = 200 kHz
–7
–2
1
dBm
–8
–6
–1
dBm
—
–70
—
dBc
Offset = 400 kHz
—
–75
—
dBc
Offset = 600 kHz
—
–80
—
dBc
RF2 Reference Spurs
Offset = 200 kHz
—
–75
—
dBc
Offset = 400 kHz
—
–80
—
dBc
Offset = 600 kHz
—
–80
—
dBc
Power Up Request to Synthesizer
Ready Time, RF1, RF2, IF2
tpup
Figures 4, 5
—
140
—
µs
Power Down Request to Synthesizer Off tpdn
Time3
Figures 4, 5
—
—
100
ns
Notes:
1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 550 MHz for all parameters unless otherwise noted.
2. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs.
3. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply
current equal to IPWDN.
8
Rev. 1.1