SI5338K View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI5338K

I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Silicon Laboratories 

Si5338

Table 5. Performance Characteristics

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min Typ

PLL Acquisition Time

tACQ

—

—

PLL Lock Range

fLOCK

5000 —

PLL Loop Bandwidth

MultiSynth Frequency

Synthesis Resolution

fBW

—

1.6

fRES

Output frequency < Fvco/8

0

0

CLKIN Loss of Signal Detect

tLOS

Time

—

2.6

CLKIN Loss of Signal Release

Time

tLOSRLS

0.01 0.2

PLL Loss of Lock Detect Time

tLOL

—

5

Max

25

—

—

1

5

1

10

Unit

ms

ppm

MHz

ppb

µs

µs

ms

POR to Output Clock Valid

(Pre-programmed Devices)

tRDY

—

—

2

ms

Input-to-Output Propagation

Delay

Output-Output Skew

POR to I2C Ready

tPROP

tDSKEW

Buffer Mode

(PLL Bypass)

Rn divider = 11

—

2.5

—

ns

—

—

100

ps

—

—

15

ms

Programmable Initial

Phase Offset

POFFSET

–45

—

+45

ns

Phase Increment/Decrement

Accuracy

PSTEP

—

—

20

ps

Phase Increment/Decrement

Range

PRANGE

–45

—

+45

ns

Frequency range for phase

increment/decrement

fPRANGE

—

—

3502

MHz

Phase Increment/Decrement

PUPDATE

Pin control2,3

667

—

—

ns

Update Time

MultiSynth output >18 MHz

Notes:

1. Outputs at integer-related frequencies and using the same driver format. See "3.9.3. Initial Phase Offset" on page 24.

2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept

between 5 MHz and Fvco/8.

3. Update rate via I2C is also limited by the time it takes to perform a write operation.

4. Default value is 0.5% down spread.

5. Default value is ~31.5 kHz.

6

Rev. 0.6

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