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SIM3C134 View Datasheet(PDF) - Silicon Laboratories

Part Name
Description
Manufacturer
SIM3C134 Datasheet PDF : 90 Pages
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SiM3C1xx
Table 3.2. Power Consumption
Parameter
Symbol
Test Condition
Min Typ Max Unit
Digital Core Supply Current
Normal Mode2,3,4,5—Full speed
IDD
with code executing from Flash,
peripheral clocks ON
FAHB = 80 MHz,
FAPB = 40 MHz
FAHB = FAPB = 20 MHz
33 36.5 mA
— 10.5 13.3 mA
FAHB = FAPB = 2.5 MHz
— 2.0 3.8 mA
Normal Mode2,3,4,5—Full speed
IDD
with code executing from Flash,
peripheral clocks OFF
FAHB = 80 MHz,
FAPB = 40 MHz
FAHB = FAPB = 20 MHz
22 24.9 mA
7.8
10
mA
Power Mode 12,3,4,6—Full speed
IDD
with code executing from RAM,
peripheral clocks ON
FAHB = FAPB = 2.5 MHz
FAHB = 80 MHz,
FAPB = 40 MHz
FAHB = FAPB = 20 MHz
— 1.2
3
mA
— 30.5 35.5 mA
8.5
mA
Power Mode 12,3,4,6—Full speed
IDD
with code executing from RAM,
peripheral clocks OFF
FAHB = FAPB = 2.5 MHz
FAHB = 80 MHz,
FAPB = 40 MHz
FAHB = FAPB = 20 MHz
1.7
mA
20
23 mA
5.3
mA
Power Mode 22,3,4—Core halted
IDD
with peripheral clocks ON
FAHB = FAPB = 2.5 MHz
FAHB = 80 MHz,
FAPB = 40 MHz
1.0
mA
19
22 mA
FAHB = FAPB = 20 MHz
7.8
mA
Power Mode 32,3
FAHB = FAPB = 2.5 MHz
1.3
mA
IDD
VDD = 1.8 V, TA = 25 °C
— 175 —
µA
VDD = 3.0 V, TA = 25 °C
— 250 —
µA
Notes:
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
Rev.1.0
7

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