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SIM3C134 View Datasheet(PDF) - Silicon Laboratories

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SIM3C134 Datasheet PDF : 90 Pages
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SiM3C1xx
Table 3.2. Power Consumption (Continued)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Power Mode 92,3—Low Power
IDD
Shutdown with VREG0 disabled,
powered through VDD and VIO
RTC Disabled,
VDD = 1.8 V, TA = 25 °C
RTC w/ 16.4 kHz LFO,
VDD = 1.8 V, TA = 25 °C
85
nA
— 350 —
nA
RTC w/ 32.768 kHz Crystal, — 620 —
nA
VDD = 1.8 V, TA = 25 °C
RTC Disabled,
VDD = 3.0 V, TA = 25 °C
— 145 —
nA
RTC w/ 16.4 kHz LFO,
VDD = 3.0 V, TA = 25 °C
— 500 —
nA
RTC w/ 32.768 kHz Crystal, — 800 —
nA
VDD = 3.0 V, TA = 25 °C
Power Mode 92,3—Low Power
IVREGIN
RTC Disabled,
— 300 —
nA
Shutdown with VREG0 in low-
VREGIN = 5 V, TA = 25 °C
power mode, VDD and VIO pow-
ered through VREG0 (Includes
RTC w/ 16.4 kHz LFO,
— 650 —
nA
VREG0 current)
VREGIN = 5 V, TA = 25 °C
RTC w/ 32.768 kHz Crystal, — 950 —
nA
VREGIN = 5 V, TA = 25 °C
VIOHD Current (High-drive I/O dis- IVIOHD
abled)
HV Mode (default)
LV Mode
— 2.5
5
µA
2
nA
Notes:
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
8
Rev.1.0

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