SIP11206DQP-T1-E3 View Datasheet(PDF) - Vishay Semiconductors

Part Name

Description

Manufacturer

SIP11206DQP-T1-E3

Half-Bridge Controller with Primary MOSFET Drivers for Intermediate Bus Converters

Vishay Semiconductors 

SiP11206

Vishay Siliconix

CIRCUIT FOR FREQUENCY SYNCHRONIZATION

SYNC IN

220 pF 100

2N3904

1k

Cosc

SiP11206

DETAILED OPERATIONAL DESCRIPTION

Start Up

The controller supply (VCC) is linearly regulated up to its

target voltage VREG by the on chip pre-regulator circuit.

During power up with VINDET ramping up from 0, the VCC

capacitor minimum charge current is 20 mA and the

pre-regulator voltage is typically 9.3 V. As VINDET exceeds

VREF, the DL/DH outputs are capable of driving 3 nF

MOSFET gate capacitances and hence the pre-regulator

load regulation can easily handle 120 µA to 20 mA load step

with a typical load regulation of 1 %. Current into the external

VCC capacitor is limited to typically 20 mA by the internal

pre-regulator unless an external power source is connected

to VCC pin. This source may be a DC supply or from VIN by

connecting a PNP pass transistor between VIN and VCC. The

VCC pin is protected by a 20 mA clamp when this pin exceeds

14.5 V. The clamp turns on when VCC is between 14.5 V and

16 V. When VCC exceeds the UVLO voltage (UVLOH) a soft

start cycle of the switch mode supply is initiated. The VCC

supply continues to be charged by the pre-regulator until VCC

equals VREG. During this period, between UVLOH and VREG,

excessive load may result in VCC falling below UVLOH and

stopping switch mode operation. This situation is avoided by

the hysteresis between VREG and UVLO Off-Threshold level

UVLOL.

PWM Operation

During startup, DL always turns on before DH and both

switch on and off at half the oscillator frequency. The driver

duty cycle increases as SS voltage increases, since the SS

comparator sets the ON pulse width by comparing the SS

ramp voltage with the oscillator ramp voltage. When SS

ramp reaches a voltage that equals to RDB voltage, the PWM

comparator, which compares RDB voltage to the oscillator

ramp, takes over and the maximum duty cycle is now set by

the oscillator ramp and RDB voltage. Mathematically, the

total duty cycle is determined by the following formula:

DTOTAL = RDB/ROSC

And the duty cycle on DL or DH will be approximately half of

DTOTAL. Please note that due to oscillator comparator

overshoot the exact duty cycle calculated using above

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formula may be slightly different. The PWM operation during

start up can be better understood by referring to "Timing

diagram and soft start duty cycle control" graph. The soft

start completion voltage at SS pin is clamped above the

internal ramp waveform's upper turning point.

Soft Start

The soft start circuit plays an important role in protecting the

controller. At startup it prevents high in-rush current. During

a normal start-up sequence (VCS < VMOC. VCS is the voltage

at CS pin), or following any event that would cause a hiccup-

and-soft-start sequence, CSS will be charged from about 0 V

to a final voltage of 4.8 V at a 20 µA rate. As the voltage on

the CSS rises towards the final voltage, the maximum

permitted DL and DH duty cycles will increase from 0 % to a

maximum defined by the RDB resistor.

When a mild fault condition is detected (VCS = VMOC), CSS

goes into a hiccup mode until fault condition is removed. The

hiccup is activated when CSS discharges to 0.85 VSS at

20 µA and subsequently at 0.4 µA until the fault condition is

removed. Refer to "Fault Conditions and Responses" for

details.

Fault Conditions and Responses

The faults that can cause a hiccup-and-retry cycle are

moderate over-current (MOC), severe over-current (SOC),

chip level UVLO, system level UVLO, and over temperature

protection (OTP).

Prior to detailing the various fault conditions and responses,

some definitions are given:

1. A complete switching period, T, consists of two oscillator

cycles, TDL and TDH.

2. TDL (TDH) is the oscillator cycle during which the DL (DH)

output is in the high state.

3. T is defined as starting at the beginning of TDL, and

terminating at the end of TDH.

Response to MOC Faults (VMOC < VCS < VSOC):

Once SiP11206 has completed a normal soft-start cycle, VSS

will be clamped at 4.5 V, allowing the maximum possible duty

cycle on DL and DH.

Document Number: 69232

S-81795-Rev. C, 04-Aug-08

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