SIP11206DQP-T1-E3 View Datasheet(PDF) - Vishay Semiconductors

Part Name

Description

Manufacturer

SIP11206DQP-T1-E3

Half-Bridge Controller with Primary MOSFET Drivers for Intermediate Bus Converters

Vishay Semiconductors 

If an MOC fault occurs following the start-up (due to a

condition such as an excessive load on the converter’s

output), SiP11206 will respond by gradually reducing the

available maximum duty cycle of its DL and DH outputs each

to be equal to approximately 42 % of their possible 47 %

maximum values. This is before any effects of deadtime

introduced by RDB are added in. This reduction in available

maximum duty cycle is achieved by reducing the voltage on

the SS pin to 4 V, as follows:

1. If VMOC < VCS < VSOC at any time during TDL, a current

of 20 µA will be drawn out of the SS pin until the

beginning of the next TDL.

2. If the voltage on the SS pin remains above the value that

would allow an available maximum DL and DH duty cycle

of 42 %, SiP11206 will continue operating.

3. If the voltage on the SS pin goes below the value that

would allow an available maximum DL and DH duty cycle

of 42 %, a hiccup interval is started, during which both DL

and DH are held in their low states.

4. The SS pin is discharged towards 0 V by a 400 nA sink

current.

5. The hiccup interval is terminated when the SS pin is

discharged to 0.25 V.

After the above actions have been taken switching on the DL

and DH outputs will then resume with a normal soft-start

cycle.

Response to MOC faults is enabled after the successful

completion of any normal soft-start cycle.

Response to SOC Faults (VCS > VSOC):

This is an immediate, single-cycle response over current

shutdown, followed by a hiccup delay and a normal soft-start

cycle. Since this is a gross fault protection mechanism, its

triggering mechanism is asynchronous to the timing of TDL

and TDH.

1. If VCS > VSOC, a hiccup interval is started, during which

both DL and DH are held in their low states.

2. The SS pin is discharged towards 0 V by a 400 nA sink

current.

3. The hiccup interval is terminated when the SS pin is

discharged to 0.25 V.

4. Switching on the DL and DH outputs will then resume

with a normal soft-start cycle.

Severe over current response is enabled at all times,

including the initial ramp-up period of the soft-start pin. This

allows SiP11206 to provide rapid fault protection for the

converter’s power train.

Immediate Response to UVLO Faults:

The under voltage protection conditions at converter-level

(VINDET pin UVLO) and chip-level (VCC UVLO) will

immediately trigger a shutdown-and-retry SS response, with

the restart requirements being that:

Document Number: 69232

S-81795-Rev. C, 04-Aug-08

SiP11206

Vishay Siliconix

1. The SS pin has been discharged at a 20 µA rate to the

0.25 V level.

2. The affected supply has recovered to its turn-on

threshold.

Once these conditions are met, switching will resume with a

normal soft-start cycle. Response to UVLO faults is enabled

at all times, including the initial ramp-up period of the soft-

start pin.

Immediate Response to an OTP Condition:

Failure of the application circuit to provide an external

voltage to the VCC pin above the VREG level may result in an

OTP condition (TJ > OTPON). Other conditions, such as

excessive ambient temperature or, where applicable, failure

of airflow over the DC-DC converter circuit, can also trigger

an OTP condition. An OTP condition will immediately trigger

a shutdown-and-retry soft start response, with the restart

requirements being that:

1. The SS pin has been discharged at a 20 µA rate to the

0.25 V level.

2. The chip junction temperature has fallen below the lower

OTP threshold.

Once these conditions are met, switching will resume with a

normal soft-start cycle. Response to the OTP condition is

enabled at all times, including the initial ramp-up period of the

soft-start pin.

Reference

The reference voltage of SiP11206 is set at 3.3 V at VREF

pin. This pin should be decoupled externally with a 0.1 µF to

1 µF capacitor to GND. Up to 5 mA may be drawn internally

from this reference to power external circuits. Note that if the

VINDET pin is pulled below 0.55 V (typical), the reference will

be turned off, and SiP11206 will enter a low-power "standby"

mode. During startup or when VREF is accidentally shorted to

ground, this pin has internal short circuit protection limiting

the source current to 50 mA. VREF load regulation for 5 mA

step is typically 0.45 %.

Oscillator

The oscillator is designed to operate from 200 kHz to 1 MHz

with temperature stability within 15 %. This operating

frequency range allows the converter to minimize the

inductor and capacitor size, improving the power density of

the converter. The oscillator frequency, and therefore the

switching frequency, is programmable by the value of

resistor and capacitor connected to the ROSC and COSC pins

respectively. Note that the switching frequency at pins DL

and DH is half of the oscillator frequency, i.e., the DL output

will be active during one oscillator cycle, and the DH during

the next oscillator cycle.

VINDET

The VINDET pin controls several modes of operation and the

modes of operation are controlled by shutdown (VSD) and

under voltage (VUV) comparators (see block diagram). When

the IC is powered solely by VIN and VINDET is less than VSDH

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