SM8951A View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
SM8951A Datasheet PDF : 16 Pages
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SyncMOS Technologies International, Inc.
SFR Memory Map
SM8951A/8952A
8-Bits Micro-controller
With 4/8KB flash embedded
$F8
$F0 B
$E8
$E0 ACC
$D8
$D0 PSW
$C8 T2CON
RC2L
RC2H
TL2
TH2
$C0
$B8 IP
$B0 P3
$A8 IE
$A0 P2
$98 SCON
SBUF
$90 P1
$88 TCON
TMOD
TL0
TL1
TH0
TH1
$80 P0
SP
DPL
DPH
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
SCONF
$BF
$B7
$AF
$A7
WDTC
$9F
$97
$8F
PCON
$87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8951A/8952A
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The
WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover from abnormal software condition.
The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by
software periodically clearing the WDT counter.
The SM8951/8952 WDT has selectable divider input for the time base source clock. To select the divider input, the
setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0
automatically when SM8958A been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the
content of the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice contact your sales representatives for the most recent information.
5
Ver 2.1 SM8951A/8952A 08/2006
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