T89C51RD2
9.5.6. External Data Memory Read Cycle
ALE
PSEN
RD
PORT 0
PORT 2
ADDRESS
OR SFR-P2
TLLDV
TWHLH
TLLWL
TRLRH
TLLAX
A0-A7
TAVWL
TAVDV
TRLAZ
TRHDX
DATA IN
ADDRESS A8-A15 OR SFR P2
TRHDZ
9.5.7. Serial Port Timing - Shift Register Mode
Table 44. Symbol Description
Symbol
Parameter
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Table 45. AC Parameters for a Fix Clock
-M
-L
Min
Max
Min
Max
300
300
200
200
30
30
0
0
117
117
Units
ns
ns
ns
ns
ns
81
Rev. F - 15 February, 2001