SP3203CY View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
Manufacturer
SP3203CY
Signal Processing Technologies
SP3203CY Datasheet PDF : 15 Pages
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duces –VCC in the negative terminal of C1, which
is applied to the negative side of capacitor C2.
Since C2+ is at VCC, the voltage potential across
C2 is 2 times VCC.
VDD Transfer-Phase 4 (Figure 16)
The fourth phase of the clock connects the nega-
tive terminal of C2 to GND, and transfers this
positive generated voltage across C2 to C4, the
VDD storage capacitor. This voltage is regulated
to +5.5V. At this voltage, the internal oscillator
is disabled. Simultaneous with the transfer of the
voltage to C4, positive side of capacitor C1 is
switched to VCC and the negative side is con-
nected to GND, allowing the charge pump cycle
to begin again. The charge pump cycle will
continue as long as the operational conditions for
the internal oscillator are present.
Since both V+ and V– are separately generated
from VCC, in a no–load condition, V+ and V– will
be symmetrical. Older charge pump approaches
that generate V– from V+ will show a decrease in
the magnitude of V– compared to V+ due to the
inherent ineffiencies in the design.
The clock rate for the charge pump is typically
operates at 250kHz. The external capacitors are
usually 0.1µF with a 16V breakdown voltage
rating.
VL Supply Level
Current RS-232 serial tranceivers are designed
with fixed 5V or 3.3V TTL input/output voltages
levels. The VL function in the SP3203 allows the
end user to set the TTL input/output voltage
levels independent of VCC. By connecting VL to
the main logic bus of system, the TTL input/
output limits and threshold are reset to interface
with the on board low voltage logic circuity.
Capacitor Selection Table:
VCC (V)
3.0 to 3.6
C1 (µF)
0.1
C2-C4(µF)
0.1
4.5 to 5.5
0.047
0.33
3.0 to 5.5
0.22
1
Date: 02/24/05
SP3203, 3V, RS232 Serial Transceiverwith Logic Selector and 15kV ESD
10
© Copyright 2005 Sipex Corporation
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