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SP5024DP View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name
Description
Manufacturer
SP5024DP
ZARLINK
Zarlink Semiconductor Inc ZARLINK
SP5024DP Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
SP5024
ELECTRICAL CHARACTERISTICS (continued)
Characteristic
Symbol Pin
Min.
Value
Typ.
Units
Max.
Conditions
Port and Lock sink current
Port leakage current
Lock leakage current
Varactor Drive Amp Disable
Charge Pump Disable
6 - 9,11
6-9
11
10
4
10
-350
-350
mA VOUT = 0.7V
10
µA VOUT = 13.2V
10
µA VOUT = VCC
µA VIN = <0V
µA VIN = <0V
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE = 0V
Parameter
Supply voltage
Prescaler inputs
Output ports
Pin
Pin
SP5024 SP5024
S
14
12
15, 16 13, 14
6-9
6-9
Total port output current
6-9
6-9
Prescaler DC offset
15, 16 13, 14
Loop amplifier DC offset
1, 18 1, 16
Crystal oscillator DC offset
2
2
Data bus inputs
4, 5 ,10 4, 5 ,10
Storage temperature
Junction temperature
DP 18 thermal resistance, chip-to-ambient
DP 18 thermal resistance, chip-to-case
MP 16 thermal resistance, chip-to-ambient
MP 16 thermal resistance, chip-to-case
Power consumption at 5V
Value
Min. Max.
Units
Conditions
-0.3
-6
V
2.5 Vp-p
-0.3
14
V Port in off state
-0.3
6
V Port in on state
50 mA
-0.3 VCC+0.3 V
-0.3 VCC+0.3 V
-0.3 VCC+0.3 V
-0.7 VCC+0.3 V
-55 +125 °C
With VCC applied
+150 °C
78 °C/W
24 °C/W
111 °C/W
41 °C/W
275 mW All ports off
RF IN
RF IN
PRE
AMP
48
PRESCALER
14/15 BIT
FPD
PROGRAMMABLE
DIVIDER
PHASE
COMP
F
FCOMP
4640/
512
OSC
4MHz
VCC
CRYSTAL
CLOCK
DATA
ENABLE
MODE
SELECT
DATA
DATA
INPUT
CLOCK
INTERFACE
MODE SELECT
14/15 BIT LATCH
DIVIDER RATIO
CHARGE
PUMP
CONTROL
OUTPUT
BUFFER
CPDIS
VADIS
LOCK
DETECT
CHARGE
PUMP
AMP
DRIVE/VARICAP
OUTPUT
VEE
P4 P3 P2 P1
LOCK
Fig.2 Block diagram
3

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