SP7545 View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
Manufacturer
SP7545 Datasheet PDF : 4 Pages
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SPECIFICATIONS (continued)
(TA=25°C; VDD =+5V, VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER
MIN. TYP. MAX.
UNIT
DIGITAL INPUTS
Logic Levels
VIH
VIL
Input Current
Input Capacitance
Bits 1—12
WR, CS
Coding
Unipolar
Bipolar
POWER REQUIREMENTS
Supply Current
2.4
VDD
2.4
13.5
VDD
13.5
-0.3
0.8
0.8
-0.3
1.5
1.5
±1.0
±10
5
20
Binary
Offset Binary
2.0
2.0
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
µA
µA
pF
pF
mA
mA
0.5
mA
mA
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
Commercial
0
+70
°C
Industrial
-40
+85
°C
Storage Temperature
-65
+150
°C
Package
20–pin Plastic DIP
20–pin Plastic LCC
CONDITIONS
VDD = +5V
VDD = +5V; Note 5
VDD = +15V
VDD = +15V; Note 5
VDD = +5V
VDD = +5V; Note 5
VDD = +15V
VDD = +15V; Note 5
VIN = 0V or VDD
Note 5 and 9
VIN = 0; Note 5 and 8
All digital inputs VIL or VIH
Note 5; all digital inputs
VIL or VIH
Note 18
Note 5 and 18
Notes and Cautions:
1. Do not apply voltages higher than VDD or less than GND potential on any terminal other than VREF or VRFB.
2. The digital inputs are diode-clamp protected against ESD damage. However, permanent damage may
occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all
times until ready to use.
3. Use proper anti-static handling procedures.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation at or above these specifications is not
implied. Exposure to the above maximum rated conditions for extended periods may affect device
reliability.
5.
From TMIN to TMAX.
6. End-point linearity
7. Differential Non-linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
8. Guaranteed by design, but not production tested.
9. Logic inputs are MOS gates. IIN typically is less than 1nA @ 25°C.
10. AC performance characteristics are included for design guidance only and are subject to sample testing
only.
11. RL = 100Ω, CEXT = 13pF; all data inputs 0V to VDD or VDD to 0V; from 50% digital input change to 90% of
final analog output.
12. Settling to ±0.01% FSR (strobed); all data inputs 0V to VDD or VDD to 0V.
13. VREF = 0V, DAC register alternatively loaded with all 0’s and all 1’s.
14. VREF = 20VP-P; F = 10kHz sinewave.
15. VREF = 20VP-P; F = 1kHz sinewave.
16. Measured using internal feedback resistor with DAC loaded with all 1’s.
17. All digital inputs = 0V.
18. All digital inputs 0V or VDD.
Corporation
SIGNAL PROCESSING EXCELLENCE
177
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