SPCA751A-P101 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SPCA751A-P101

single chip signal processor optimized for MPEG audio decoding and voice recording

Unspecified 

Preliminary

SPCA751A-P101

Function Description

The SPCA751A is a single-chip CMOS microprocessor optimized for real-time MPEG audio decoding and

speech/audio recording.

SPCA751A decodes the encoded MPEG audio data according to the commands passed through the Serial

Control/Data I/O Interface by the host processor, the host processor can also check the status of decoding process by

the use of this interface. Refer to Programming Guide for command definitions

In the digital recorder mode, speech/Audio is sampled at 8Khz by the on-chip ADC into 10-bit digital words, after

encoding, the datum is compressed into a data rate of 4.8Kbps or 32Kbps.

Decoded audio PCM data are output to external DAC through a programmable normal/I2S PCM interface, this

interface is compliant to most of the common audio DACs.

The embedded PLL is capable of providing the 27 MHz system clock derived from a 16.934MHz clock source

! Serial Control/Data I/O Interface

The host controller uses this interface to transfer MPEG bit-stream with the SPCA751A and to command the

SPCA751A during the recording/decoding process. This interface consists of seven pins:

Host

Controller

FCEB1

FCEB2

SCLK

RFS1

TFS1

DR1

DT1

SPCA

751A

Pin # 12

Pin # 13

Pin # 44

Pin # 1

Pin # 2

Pin # 3

Pin # 4

FCEB2

FCEB1

SCLK1

DT1

TFS1

DR1

RFS1

Frame Decoded Indicator generated by the SPCA751A

Data Request Flag generated by the SPCA751A

Bit Clock controlled by the host processor

Data from the SPCA751A to the host processor

Transmit Frame Synchronization controlled by the host processor

Data from the host processor to the SPCA751A

Receive Frame Synchronization controlled by the host processor

" FCEB1 - Data Request Flag

The FCEB1 flag generated by the SPCA751A informs the status of the decoding/encoding process. When FCEB1

is high, it indicates that the SPCA751A is ready to receive data/command or to transfer data, the host processor is

allowed to start the communication; When FCEB1 is low, the SPCA751A is busy processing internally and no I/O tasks

could be taken, the commands sent by the host processor during low FCEB1 are not accepted by the SPCA751A and

may cause the SPCA751A run into an unknown state.

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