SPCA751A-P101 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SPCA751A-P101

single chip signal processor optimized for MPEG audio decoding and voice recording

Unspecified 

Preliminary

SPCA751A-P101

" FCEB2 - Frame Decoded Indicator

Each time the SPCA751A has decoded one frame (512 bytes) of data, it changes the state of FCEB2 (either high

to low or low to high) and progresses to the next frame. By counting the number of state-changes, the host processor

is able to know the time elapsed in decoding.

" Host Command

The host commands consist of 8-bit command and 8-bit ID, totally 16-bit long. (Refer to the SPCA751A

Programming Guide for command definitions) At the falling edges of SCLK1, the SPCA751A checks whether the RFS1

is high. Once it is high, the 16-bit long command is sampled at the following 16 consecutive falling edges of SCLK1

with MSB first. After the LSB is sent, the host processor should send at least one more cycle of SCLK1 to the

SPCA751A.

SCLK1

RFS1

DR1

TFS

TFH

b15

TSCLK

TDS

TDH

b14

b1

b0

" Host processor writes 512 bytes to the SPCA751A

At the falling edges of SCLK1, the SPCA751A checks whether the RFS1 is high. Once it is high, the 512-byte long

data is sampled at the following 512x8 consecutive falling edges of SCLK1. RFS1 should remain high before the MSB

of the last word. After the LSB of the last word is sent, the host processor should send at least three more cycles of

SCLK1 to the SPCA751A.

SCLK1

RFS1

TFS

DR1

Timing Requirements

b15

TSCLK

TDS

TDH

b14

255 words

TFH

b0

b15

b0

Last word

PARAMETER

TFS

TFH

TDS

TDH

TSCLK

RFS1 setup before SCLK1 falls low

RFS1 hold after SCLK1 falls low

DR1 setup before SCLK1 falls low

DR1 hold after SCLK1 falls low

SCLK1 period

MIN.

2

2

3

3

16

MAX.

*

UNIT

ns

ns

ns

ns

ns

* The maximum period of SCLK1 depends on the sampling rate of the decoded data, too long a SCLK1

period makes the real-time decoding impossible.

4

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