SSD1818ATR1 View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD1818ATR1

104 x 65 STN LCD Segment / Common Driver with Controller

Solomon Systech  

D7-D0

These pins are the 8-bit bi-directional data bus in parallel interface mode. D7 is the MSB while D0 is the

LSB. When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK).

VDD

These pins are the Chip’s Power Supply pins. These pins are also act as the reference for the DC-DC

Converter output and the LCD driving voltages.

VSS

These pins are the grounding of the chip. They are also act as the reference for the logic pins.

VSS1

These pins are the inputs for internal DC-DC converter. The voltage of generated, VEE, equals to the

multiple factors times the potential different between these pins, VSS1, and VDD. The multiple factors, 2X,

3X, 4X or 5X are selected by different connections of the external capacitors. All voltage levels are

referenced to VDD.

Note: the potential of Vss1 at this input pin must lower than or equal to VSS.

VEE

This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the

internal DC-DC converter. The internal DC-DC converter is turned on when the internal voltage booster

option is enabled. Please refer to the Set Power Control Register command for detail description.

When using internal DC-DC converter as voltage generator, voltage at this pin is used for internal

referencing only. It CANNOT be used for driving external circuitry.

C1P, C1N, C2N, C2P C3N and C4N

When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these

pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X, 4X or

5X. For detailed connections, please refer to the voltage converter section in the functional block

description.

VL2, VL3, VL4 and VL5

These pins are outputs with voltage levels equal to the LCD driving voltage. All these voltage levels are

referenced to VDD. The voltage levels can be supplied externally or generated by the internal bias divider.

The bias divider is turned on when the output op-amp buffers are enabled. Please refer to the Set Power

Control Register command for detail description.

The voltage potential relationship of these pins are given as:

VDD > VL2 > VL3 > VL4 > VL5 > VL6

In addition, assume the bias factor is known as a,

VL2 - VDD = 1/a * (VL6 - VDD)

VL3 - VDD = 2/a * (VL6 - VDD)

VL4 - VDD = (a-2)/a * (VL6 - VDD)

VL5 - VDD = (a-1)/a * (VL6 - VDD)

VL6

This pin outputs the most negative LCD driving voltage level. The VL6 can be supplied externally or

generated by the internal regulator. Please refer to the Set Power Control Register command for detail

description.

SSD1818A

Rev 1.2 P 11/47 Mar 2004

Solomon Systech

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