2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
CE#
SCK
SO
SI
HOLD#
THHH
THLS
THZ
THLH
THHS
TLZ
FIGURE 17: HOLD TIMING DIAGRAM
VDD
VDD Max
Chip selection is not allowed.
All commands are rejected by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
1231 F17.0
FIGURE 18: POWER-UP TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
19
Time
1231 F18.0
S71231-04-000
6/04