SST25VF020B View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST25VF020B

2 Mbit SPI Serial Flash

Silicon Storage Technology 

Data Sheet

Status Register

The software status register provides status on whether the

flash memory array is available for any Read or Write oper-

ation, whether the device is Write enabled, and the state of

the Memory Write protection. During an internal Erase or

2 Mbit SPI Serial Flash

SST25VF020B

Program operation, the status register may be read only to

determine the completion of an operation in progress.

Table 3 describes the function of each bit in the software

status register.

TABLE 3: Software Status Register

Bit Name

0 BUSY

1 WEL

2 BP0

3 BP1

4:5 RES

6 AAI

7 BPL

Function

1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

1 = Device is memory Write enabled

0 = Device is not memory Write enabled

Indicates current level of block write protection (See Table 5)

Indicates current level of block write protection (See Table 5)

Reserved for future use

Auto Address Increment Programming status

1 = AAI programming mode

0 = Byte-Program mode

1 = BP1, BP0 are read-only bits

0 = BP1, BP0 are read/writable

Default at

Power-up

0

0

1

1

0

0

Read/Write

R

R

R/W

R/W

N/A

R

0

R/W

T3.0 1417

Software Status Register 1

The Software Status Register 1 is an additional register

that contains Top Sector and Bottom Sector Protection bits.

These register bits are read/writable and determine the

lock and unlock status of the top and bottom sectors.

Table 4 describes the function of each bit in the Software

Status Register 1.

TABLE 4: Software Status Register 1

Bit Name

0:1 RES

2 TSP

3 BSP

4:7 RES

Function

Reserved for future use

Top Sector Protection status

1 = Indicates highest sector is write locked

0 = Indicates highest sector is Write accessible

Bottom Sector Protection status

1 = Indicates lowest sector is write locked

0 = Indicates lowest sector is Write accessible

Reserved for future use

Default at

Power-up

0

0

Read/Write

N/A

R/W

0

R/W

0

N/A

T4.0 1417

Busy

The Busy bit determines whether there is an internal Erase

or Program operation in progress. A “1” for the Busy bit indi-

cates the device is busy with an operation in progress. A “0”

indicates the device is ready for the next valid operation.

Write Enable Latch (WEL)

The Write-Enable-Latch bit indicates the status of the inter-

nal memory Write Enable Latch. If the Write-Enable-Latch

bit is set to “1”, it indicates the device is Write enabled. If the

bit is set to “0” (reset), it indicates the device is not Write

enabled and does not accept any memory Write (Program/

Erase) commands. The Write-Enable-Latch bit is automati-

cally reset under the following conditions:

©2010 Silicon Storage Technology, Inc.

6

S71417-02-000

04/10

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