SST25VF040B View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
SST25VF040B Datasheet PDF : 33 Pages
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4 Mbit SPI Serial Flash
SST25VF040B
Read (25/33 MHz)
The Read instruction, 03H, supports up to 25 MHz (for
SST25VF040B-50-xx-xxF) or 33 MHz (for SST25VF040B-
80-xx-xxE) Read. The device outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
Data Sheet
beginning (wrap-around) of the address space. Once the
data from address location 1FFFFFH has been read, the
next output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 5 for the Read sequence.
CE#
MODE 3
SCK MODE 0
0 1 2345 6 78
15 16
23 24 31 32 39 40 47 48 55 56 63 64 70
SI
03
ADD. ADD. ADD.
MSB
MSB
HIGH IMPEDANCE
SO
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1295 ReadSeq.0
FIGURE 5: Read Sequence
©2009 Silicon Storage Technology, Inc.
9
S71295-05-000
10/09
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