SST25LF040A-33-4E-QAE View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
SST25LF040A-33-4E-QAE Datasheet PDF : 26 Pages
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2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Read (20 MHz)
The Read instruction supports up to 20 MHz, it outputs the
data starting from the specified address location. The data
output stream is continuous through all addresses until ter-
minated by a low to high transition on CE#. The internal
address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address
Data Sheet
space, i.e. for 4 Mbit density, once the data from address
location 7FFFFH had been read, the next output will be
from address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
CE#
MODE 3
SCK MODE 0
0 1 2345 6 78
15 16
23 24 31 32 39 40 47 48 55 56 63 64 70
SI
03
ADD. ADD. ADD.
MSB
MSB
HIGH IMPEDANCE
SO
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1242 F04.0
FIGURE 4: READ SEQUENCE
©2006 Silicon Storage Technology, Inc.
9
S71242-05-000
1/06
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