SST25PF020B(2012) View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
SST25PF020B Datasheet PDF : 33 Pages
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SST25PF020B
4.5 Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25PF020B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-5. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-5: DEVICE OPERATION INSTRUCTIONS
Instruction
Read
High-Speed Read
4 KByte Sector-
Erase3
32 KByte Block-
Erase4
64 KByte Block-
Erase5
Chip-Erase
Byte-Program
AAI-Word-Program6
RDSR7
RDSR1
EWSR
WRSR
WREN
WRDI
RDID8
JEDEC-ID
EBSY
DBSY
Description
Read Memory
Read Memory at higher speed
Erase 4 KByte of memory array
Erase 32 KByte block of memory
array
Erase 64 KByte block of memory
array
Erase Full Memory Array
To Program One Data Byte
Auto Address Increment Program-
ming
Read-Status-Register
Read-Status-Register 1
Enable-Write-Status-Register
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
JEDEC ID Read
Enable SO to output RY/BY# status
during AAI programming
Disable SO to output RY/BY# status
during AAI programming
Op Code Cycle1
0000 0011b (03H)
0000 1011b (0BH)
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
0110 0000b (60H) or
1100 0111b (C7H)
0000 0010b (02H)
1010 1101b (ADH)
0000 0101b (05H)
0011 0101b (35H)
0101b 0000b (50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H) or
1010 1011b (ABH)
1001 1111b (9FH)
0111 0000b (70H)
1000 0000b (80H)
Address
Cycle(s)2
3
3
3
Dummy
Cycle(s)
0
1
0
Data
Cycle(s)
1 to ∞
1 to ∞
0
3
0
0
3
0
0
0
0
0
3
0
1
3
0
2 to ∞
0
0
1 to ∞
0
0
1 to ∞
0
0
0
0
0
1 or 2
0
0
0
0
0
0
3
0
1 to ∞
0
0
3 to ∞
0
0
0
0
0
0
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be pro-
grammed into the initial address [A23-A1] with A0=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
DS25135A-page 8
2012 Microchip Technology Inc.
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