SST25PF020B View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
SST25PF020B Datasheet PDF : 33 Pages
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2.0 PIN DESCRIPTION
SST25PF020B
CE#
SO
WP#
VSS
1
8
2
7
Top View
3
6
4
5
VDD
HOLD#
SCK
SI
CE# 1
SO 2
WP# 3
VSS 4
Top View
8 VDD
7 HOLD#
6 SCK
5 SI
8-Lead SOIC
25135 08-soic S2A P1.0
8-Contact WSON
25135 08-wson QA P2.0
CE# 1
SO 2
WP# 3
VSS 4
Top View
8
VDD
7 HOLD#
6 SCK
5
SI
8-Contact USON
25135 08-uson Q3A P1.0
FIGURE 2-1:
PIN ASSIGNMENTS
TABLE 2-1: PIN DESCRIPTION
Symbol Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See “Hardware End-of-Write Detection” on page 11 for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold
To temporarily stop serial communication with SPI flash memory without resetting
the device.
VDD
Power Supply
To provide power supply voltage: 2.3-3.6V for SST25PF020B
VSS
Ground
2013 Microchip Technology Inc.
DS20005135B-page 3
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