SST34HF1642D-70-4E-LPE View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST34HF1642D-70-4E-LPE

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

Silicon Storage Technology 

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Data Protection

The SST34HF16x2C/D/S provide both hardware and soft-

ware features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Hardware Block Protection

The SST34HF16x2C/D/S provide a hardware block protec-

tion which protects the outermost 8 KWord in Bank 1. The

block is protected when WP# is held low. See Figures 1

and 2 for Block-Protection location.

A user can disable block protection by driving WP# high

thus allowing erase or program of data into the protected

sectors. WP# must be held high prior to issuing the write

command and remain stable until after the entire Write

operation has completed.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate and

return to Read mode (see Figure 19). When no internal

Program/Erase operation is in progress, a minimum period

of TRHR is required after RST# is driven high before a valid

Read can take place (see Figure 18).

The Erase operation that has been interrupted needs to be

reinitiated after the device resumes normal operation mode

to ensure data integrity. See Figures 18 and 19 for timing

diagrams.

Software Data Protection (SDP)

The SST34HF16x2C/D/S provide the JEDEC standard

Software Data Protection scheme for all data alteration

operations, i.e., Program and Erase. Any Program opera-

tion requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. The SST34HF16x2C/D/S are shipped

with the Software Data Protection permanently enabled.

See Table 7 for the specific software command codes. Dur-

ing SDP command sequence, invalid commands will abort

the device to Read mode within TRC. The contents of DQ15-

DQ8 are “Don’t Care” during any SDP command

sequence.

Security ID

The SST34HF16x2C/D/S devices offer a 256-bit Security

ID space. The Secure ID space is divided into two 128-bit

segments—one factory programmed segment and one

user programmed segment. The first segment is pro-

grammed and locked at SST with a unique, 128-bit num-

ber. The user segment is left un-programmed for the

customer to program as desired. To program the user seg-

ment of the Security ID, the user must use the Security ID

Word-Program command. End-of-Write status is checked

by reading the toggle bits. Data# Polling is not used for

Security ID End-of-Write detection. Once programming is

complete, the Sec ID should be locked using the User-Sec-

ID-Program-Lock-Out. This disables any future corruption

of this space. Note that regardless of whether or not the

Sec ID is locked, neither Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-

byte command sequence with Query-Sec-ID command

(88H) at address 5555H in the last byte sequence. To exit

this mode, the Exit-Sec-ID command should be executed.

Refer to Table 7 for more details.

©2004 Silicon Storage Technology, Inc.

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S71256-00-000

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