SST49LF004C View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
SST49LF004C Datasheet PDF : 36 Pages
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Advance Information
Firmware Memory Write Cycle
4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
TABLE 5: FIRMWARE MEMORY WRITE CYCLE
Clock
Cycle
1
2
3-9
10
11-A
(A+1)
(A+2)
(A+3)
(A+4)
(A+5)
Field
Name
START
IDSEL
MADDR
MSIZE
DATA
TAR0
TAR1
RSYNC
TAR0
TAR1
Field Contents
LAD[3:0]1
1110
0000 to 1111
YYYY
KKKK
ZZZZ
1111
1111 (float)
0000
1111
1111 (float)
LAD[3:0]
Direction
IN
IN
IN
IN
IN
IN then Float
Float then OUT
OUT
OUT then Float
Float then IN
Comments
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) will be recognized. The START field contents
(1110b) indicate a Firmware Memory Write cycle.
Indicates which SST49LF00xC device should
respond. If the IDSEL (ID select) field matches the
value of ID[3:0], then that particular device will respond
to the whole bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
The MSIZE field indicates how many bytes will be
transferred during multi-byte operations.
Device supports 1, 2, and 4 Bytes write with MSIZE =
0, 1, or 2, and KKKK=0000b, 0001b, or 0010b.
A=(10+2n+1); n = MSIZE
Least significant nibble entered first.
In this clock cycle, the master (Intel ICH) has driven the
bus to all ‘1’s and then floats the bus prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.” A=(10+2n+1); n = MSIZE
The SST49LF00xC takes control of the bus during this
cycle.
A=(10+2n+1); n = MSIZE
During this clock cycle, the SST49LF00xC generates
a “ready sync” (RSYNC) and outputs the values 0000,
indicating that it has received data or a flash command.
A=(10+2n+1); n = MSIZE
In this clock cycle, the SST49LF00xC drives the bus to
all ‘1’s and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle”. A=(10+2n+1); n = MSIZE
The host resumes control of the bus during this cycle.
A=(10+2n+1); n = MSIZE
1. Field contents are valid on the rising edge of the present clock cycle.
T5.0 1292
LCLK
LFRAME#
LAD[3:0]
Start IDSEL
MADDR
MSIZE
DATA
TAR0 TAR1 RSYNC
1110b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] KKKKb D0[3:0] D0[7:4]
Dn[3:0] Dn[7:4] 1111b Tri-State 0000b TAR
1292 F04.0
FIGURE 6: FIRMWARE MEMORY WRITE CYCLE WAVEFORM
©200 Silicon Storage Technology, Inc.
14
S71292-00-000
1/06
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