ST10F168
3 - FUNCTIONAL DESCRIPTION
The architecture of the ST10F168 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem.
Figure 3 : Block Diagram
The block diagram gives an overview of the
different on-chip components and the high
bandwidth internal bus structure of the ST10F168.
256K Byte
32
Flash
memory
CPU-Core
16
16
Internal
RAM
16
6K Byte
XRAM
16
PEC
Watchdog
OSC.
+ PLL
XTAL1
XTAL2
CAN_RxD P4.5
CAN_TxD P4.6
CAN
Interrupt Controller
16
16
16
8
Port 6
8
Port 5
16
BRG
BRG
Port 3
15
Port 7
8
16
Port 8
8
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