F272-BAR-P View Datasheet(PDF) - STMicroelectronics
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Description
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F272-BAR-P Datasheet PDF : 188 Pages
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ST10F272B/ST10F272E
Electrical characteristics
Table 79. Demultiplexed bus timings (continued)
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
min.
max.
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
t38 CC
t39 SR
t41 CC
t82 CC
t83 CC
t46 SR
t47 SR
t48 CC
t49 CC
t50 CC
t51 SR
t53 SR
t68 SR
t55 CC
t57 CC
ALE falling edge to Latched
CS
Latched CS low to Valid Data
In
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS
(with RW-delay)
Address setup to RdCS,
WrCS
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay) 3
Data float after RdCS
(no RW-delay) 3
Address hold after
RdCS, WrCS
Data hold after WrCS
– 4 – tA
–
2 + tF
14 + 2tA
2 + 2tA
–
–
15.5 + tC
28 + tC
10 + tC
0
–
–
– 8.5 + tF
2 + tF
6 – tA
– 4 – tA
6 – tA
ns
16.5 +
+ tC + 2tA
–
3TCL – 21 +
+ tC + 2tA
ns
–
TCL – 10.5 + tF
–
ns
–
2TCL – 11 + 2tA
–
ns
–
TCL –10.5 + 2tA
–
ns
4 + tC
–
2TCL – 21 + tC ns
16.5 + tC
–
3TCL – 21 + tC ns
–
2TCL – 9.5 + tC
–
ns
–
–
–
16.5 + tF
3TCL – 9.5 + tC
–
ns
2TCL – 15 + tC
–
ns
0
–
ns
–
2TCL – 8.5 + tF ns
4 + tF
–
TCL – 8.5 + tF ns
–
– 8.5 + tF
–
ns
–
TCL – 10.5 + tF
–
ns
1. RW-delay and tA refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
Doc ID 11917 Rev 3
171/188
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