ST72324J2T5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324J2T5

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST72324

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

If the external RESET pulse is shorter than

tw(RSTL)out (see short ext. Reset in Figure 14), the

signal on the RESET pin may be stretched. Other-

wise the delay will not be applied (see long ext.

Reset in Figure 14). Starting from the external RE-

SET pulse recognition, the device RESET pin acts

as an output that is pulled low during at least

tw(RSTL)out.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the

microcontroller correctly, the user must ensure by

means of an external reset circuit that the reset

signal is held low until VDD is over the minimum

level specified for the selected fOSC frequency.

(see “OPERATING CONDITIONS” on page 115)

Figure 14. RESET Sequences

VDD

VIT+(LVD)

VIT-(LVD)

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

6.3.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

s Power-On RESET

s Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 14.

The LVD filters spikes on VDD larger than tg(VDD) to

avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

RUN

LVD

RESET

ACTIVE PHASE

RUN

SHORT EXT.

RESET

ACTIVE

PHASE

RUN

LONG EXT.

RESET

ACTIVE

PHASE

RUN

WATCHDOG

RESET

ACTIVE

PHASE

RUN

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

tw(RSTL)out

th(RSTL)in

tw(RSTL)out

th(RSTL)in

DELAY

tw(RSTL)out

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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