ST7265x
RESET SEQUENCE MANAGER (Cont’d)
In stand-alone mode, the 512 CPU clock cycle de-
lay allows the oscillator to stabilize and ensures
that recovery has taken place from the Reset
state.
Figure 20. Reset Delay in Stand-alone Mode
RESET
In USB mode the delay is 256 clock cycles count-
ed from when the PLL LOCK signal goes high.
The RESET vector fetch phase duration is 2 clock
cycles.
DELAY
512 x tCPU(STAND-ALONE)
FETCH VECTOR
Figure 21. Reset Delay in USB Mode
RESET
DELAY
256 x tCPU(STAND-ALONE)
PLL Startup
time (undefined)
400 µs typ.
256 x tCPU(USB) FETCH VECTOR
Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.
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