STM812 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM812

Reset Circuit

STMicroelectronics 

STM809/810/811/812

OPERATION

Reset Output

The STM809/810/811/812 MICROPROCESSOR

RESET CIRCUIT asserts a reset signal to the

MCU whenever VCC goes below the reset thresh-

old (VRST), or when the push-button reset input

(MR) is taken low (see Figure 15., page 11). RST

(active high for STM810/812) is guaranteed valid

down to VCC = 1V (0° to 70°C).

During power-up, once VCC exceeds the reset

threshold an internal timer keeps RST low for the

reset time-out period, trec. After this interval, RST

returns high.

If VCC drops below the reset threshold, RST goes

low. Each time RST is asserted, it stays low for at

least the reset time-out period. Any time VCC goes

below the reset threshold, the internal timer clears.

The reset timer starts when VCC returns above the

reset threshold. The active-low reset (RST) and

active-high reset (RST) both source and sink cur-

rent.

Push-Button Reset Input (STM811/812)

A logic low on MR asserts RST. RST remains as-

serted while MR is low, and for trec after it returns

high. The MR input has an internal 20kΩ pull-up

resistor, allowing it to be left open if not used. This

input can be driven with TTL/CMOS-logic levels or

with open-drain/collector outputs. Connect a nor-

mally open push-button switch from MR to GND to

create a manual reset function; external debounce

circuitry is not required. If the device is used in a

noisy environment, connect a 0.1µF capacitor

from MR to GND to provide additional noise immu-

nity.

Negative-Going VCC Transients

The STM809/810/811/812 are relatively immune

to negative-going VCC transients (glitches). Figure

13., page 9 shows typical transient duration ver-

sus reset comparator overdrive (for which the

STM809/810/811/812 will NOT generate a reset

pulse). The graph was generated using a negative

pulse applied to VCC, starting at 0.5V above the

actual reset threshold and ending below it by the

magnitude indicated (comparator overdrive). The

graph indicates the maximum pulse width a nega-

tive VCC transient can have without causing a re-

set pulse. As the magnitude of the transient

increases (further below the threshold), the maxi-

mum allowable pulse width decreases. Any com-

bination of duration and overdrive which lies under

the curve will NOT generate a reset signal. Typi-

cally, a VCC transient that goes 100mV below the

reset threshold and lasts 20µs or less will not

cause a reset pulse. A 0.1µF bypass capacitor

mounted as close as possible to the VCC pin pro-

vides additional transient immunity.

Valid /RST Output Down to VCC = 0V

When VCC falls below 1V, the RST (STM809/811)

output no longer sinks current, but becomes an

open circuit. In most systems this is not a problem,

as most MCUs do not operate below 1V. However,

in applications where RST output must be valid

down to 0V, a pull-down resistor may be added to

hold the RST output low. This resistor must be

large enough to not load the RST output, and still

be small enough to pull the output to ground. A

100KΩ resistor is recommended.

Note: The same situation applies for the active-

high RST of the STM810/812. A 100KΩ pull-up re-

sistor to VCC should be used if RST must remain

valid for VCC < 1.0V.

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