STV0042 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STV0042

STV0042/STV0056 APPLICATION NOTE

STMicroelectronics 

STV0042/STV0056 APPLICATION NOTE

3 - APPLICATION NOTES (continued)

- FM Deviation Selection :

This part is a programmable attenuator driven by

R5 B0-5.

- SW3-SW4-SW5 :

Those switches are used to drive the VCO either

by the Synthesizer or by the wanted subcarrier.

During the synthesis SW4 is closed, SW5 is set

to L, and SW3 is connected to bias (in order not

to have parasitic drives coming from the phase

detector).

Those switches are driven by the R06 B2 B4 (left),

R06 B2 B5 (right).

- Amplifier A and CPUMP Pin :

During the demodulation, the DC voltage cor-

responding to the VCO center frequency is

memorized in a large capacitor (about 10µF)

connected at CPUMP Pins.

To prevent the VCO from slow frequency shifts

which could be generated by current leakages,

the PLL demodulator has a DC loop which is

closed by a voltage to current amplifier A.

The output current capability of this amplifier is

low (max. ± 2µA) in order not to disturb the AC

operation of the amplifier.

c) Why an AGC Input Stage

When no selective filter (LC or ceramic) is used, the

sum of all the subcarriers is input in the phase

detector of the PLL demodulator.

Consequently a linear type of phase detector is

necessary (to avoid intermodulations); but this type

of phase detector features a gain which is propor-

tionnal to the amplitude (As) of the subcarrier to be

demodulated.

KD = α ⋅ As (3)

Refering to the relation (1), the lock range of the

PLL demodulator :

ωL = KO ⋅ K ⋅ KD = KO ⋅ K ⋅ α ⋅ As

Consequently in order to have a stable lock range,

it is important to maintain a constant amplitude of

the wanted subcarrier ; then an automatically gain

controlled stage is required.

d) Breaking Down the AGC Stage

- The AGC amplifier is controlled by two level de-

tectors, and offers a 40dB gain range.

- The first control loop built with the AGC stage and

the level detector 1, is always active (during the

synthesis and the demodulation). This loop guar-

antees that the amplitude (As) of the wanted

subcarrier does not take too small or too high

values. In doing so, the first capture is easier

when starting to demodulate.

- The second loop made of : the amplitude detec-

tor, level detector 2 and the AGC stage, is active

only during demodulation (SW3 connected to

AGC amplifier).

When operating, thanks to the higher current

capability of level detector 2, the second loop

controls the AGC amplifier.

After the PLL capture, the amplitude detector

receives all the subcarriers on one input and the

VCO signal at the other input. Due to the PLL the

VCO signal is synchronous with the wanted sub-

carrier ; consequently the average DC signal

which can be measured at AMPLOCK Pin only

depends on the amplitude of the wanted subcar-

rier (regardless the amplitude and the number of

the other subcarriers).

Finally with this second loop the amplitude of the

wanted subcarrier is constant at the input of the

phase detector.

An external RD filter is used on the AMPLOCK

Pin to reject all the AC components of the ampli-

tude detector output signal.

- SD comparator : This Subcarrier Detector com-

parator switches to high when the AMPLOCK

voltage exceeds a fixed threshold. In doing so it

detects wether a subcarrier is present at the

wanted frequency.

e) Synthesizer

This function is shared between both FM demodu-

lators.For this reason, when demodulating a stereo

pair, two successive frequency synthesis se-

quences are required.

The synthesizer used a conventional PLL solution,

in which the VCO signal frequency is divided by a

programmable N factor, and the frequency divided

signal is compared in phase with a precise fre-

quency reference (10kHz) derived from the crystal

oscillator). The output of the phase detector is a

current which charges or discharges the external

CPUMP capacitor, so that the VCO frequency con-

verges to the required frequency. The average

charge current (when fVCO is quite different from

the wanted frequency) is about 60µA. Conse-

quently the tuning speed is about

∆fVCO

∆t

≈

10.5MHz/second (C41 = 10µF)

Important Remark :

Due to its loop gain the frequency synthesizer has

a ± 10kHz accuracy.

10/37

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