STV0042 View Datasheet(PDF) - STMicroelectronics
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STV0042 Datasheet PDF : 37 Pages
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STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued)
3.1.1 - Breaking down the Baseband Video Processing Function
3.1.1.1 - Input Stage
This wide band input stage has a programmable
gain (R1 B0-5).
The gain value is selected to get a 1VPP signal at
the output (loaded with 75Ω).
Taking into account all the different gains of the
video channel (externbal and internal buffers, low
pass filters), it corresponds to a 0.4VPP signal at the
input of the de-emphasis amplifier (synchro top to
peak white (not taking into account the pre-empha-
sis spikes)).
GInput Stage
=
0.4 VPP
VT±W
VT-W : the synchro top to peak white amplitude of
the signal delivered by the tuner.
3.1.1.2 - Video Polarity Inverter
To comply with both positive video (Ku bands) and
negative video (C-band) ; a programmable inverter
is implemented in the STV42/56 to recover good
video phase.
3.1.1.3 - Video De-emphasis + External Low
Pass Filter
The video de-emphasis function is realized with a
non-inverting amplifier (see Figure 5).
Dimensionning the External Components
The required video de-emphasis law is :
F
=
K
⋅
1
+
f
f2
f : frequency
(1)
1
+
f
f1
in 625 lines systems : f2 = 1.56MHz, f1 = 312kHz
in 525 lines systems : f2 = 0.875MHz, f1 =187kHz
The AC gain of the structure can be calculated as
follow :
GAC
=
1
+
z2
z1
=
1
+
R
(R9
R9
C12
p+
1)
(2)
p : Laplace operator (p : j2πf in the frequency field)
R : R11//R10
|1/C2p| << R11 for video frequencies
With some calculations, the relation (2) can be
presented with the same shape as (1) :
(2)
⇔
(
1
+
R9
R
)
1
+
( R9
R9
(1
C12 p
+
R9
R
)
C12 p + 1 )
=
GAC
(3)
Comparing (1) and (3)
f2
f1
=
1
+
R9
R
(4)
and
f1
=
2
π
1
R9
C12
(5)
Additionnaly the DC output voltage of the de-em-
phasis amplifier is choosen in the range of 3.5 to
4.0V.
This range offers two advantages :
- limits the current consumption when hybrid type
of low pass filters are choosen, as suggested in
our typical application diagrams
(TDK SEL 5618 filter)
IOUT
DC
=
VOUT DC
R15 + R16
- When the low pass filter is built with discrete
components (L and C), there is generally the
need for a group delay compensation circuit
(see Figure 5) which implements a transistor Q.
In such a case, to offer the widest swing, the
voltage at the emitter VE should be :
VE
≈
VDD
4
≈
3V,
VE ≈ (VOUT DC - 0.7V)
The DC output voltage of the de-emphasis ampli-
fier is :
VOUT
DC
=
VIN DC
⋅
1
+
R9
R10
≈
3.7V
(6)
with VIN DC = 2.45V
Using relations (4), (5), (6), it is possible to deter-
mine all the component values.
- 625 lines systems : (VIDEEM1 Pin)
R9 = 5.1kΩ (choosen value)
⇒ C12 = 100pF, R10 = 10kΩ, R11 = 1.5kΩ,
C13 ≥ 10µF
- 525 lines systems (see the PAL/NTSC typical
application diagram, Pin VIDEEM2)
R14 = 5.6kΩ (choosen value)
⇒ C14 = 100pF, R13 = 10kΩ, R12 = 1.5kΩ,
C15 ≥ 10µF
Remark :
In order not to be to sensitive to potential crosstalk
with the 22kHz tone signal which can be generated
from Pin VIDEEM2/22kHz, it is possible to lower
the impedance of the de-emphasis network ; for
exemple by choosing R9 ≈ 2.2kΩ. In this case, it is
required to add a resistor (≈ 2.7kΩ) between the
UNCL.DEEM Pin and ground. With R9 < 2.2kΩ, the
power consumption of the de-emphasis amplifier
becomes important.
5/37
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