SX1239 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

SX1239

Low Power Integrated UHF Receiver

Semtech Corporation 

SX1239

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

3.3.4. Lock Time

PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc.

When using the built-in sequencer, the SX1239 optimizes the startup time and automatically starts the receiver when the

PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given in the specification,

or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking range.

When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately:

TPLLAFC

=

---------5----------

PLLBW

In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of magnitude for the

expected lock times.

3.3.5. Lock Detect Indicator

A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its

locking range. Please refer to Table 17 and Table 18 to map this interrupt to the desired pins.

3.4. Receiver Description

The SX1239 features a digital receiver with the analog to digital conversion process being performed directly following the

LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is,

however, demodulated by a low-IF architecture. All the filtering, demodulation, gain control, synchronization and packet

handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected. The

receiver is also capable of automatic gain calibration in order to improve precision on RSSI measurements.

3.4.1. Block Diagram

Rx Calibration

Reference

LNA

RFIN

Single to

Differential

Σ/Δ

Mixers Modulators

Channel

Filter

DC

Cancellation

Complex

Filter

CORDIC

Phase

Output

FSK

Demodulator

Local

Oscillator

AFC

AGC

Bypassed

in FSK

Module

Output

RSSI

OOK

Demodulator

Figure 5. Receiver Block Diagram

The following sections give a brief description of each of the receiver blocks.

Rev 3 - Jan 2011

Page 17

www.semtech.com

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