SX1239 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

SX1239

Low Power Integrated UHF Receiver

Semtech Corporation 

SX1239

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

This product datasheet contains a detailed description of the SX1239 performance and functionality. Please consult the

Semtech website for the latest updates or errata.

Refer to section 9 of this document to identify chip revisions.

1. General Description

The SX1239 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The

SX1239's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high

level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended

for use as high-performance, low-cost FSK and OOK RF receiver for robust frequency agile RF links, and where stable

and constant RF performance is required over the full operating range of the device down to 1.8V.

The SX1239 is intended for applications over a wide frequency range, including the 433 MHz and 868 MHz European and

the 902-928 MHz North American ISM bands. Coupled with a very aggressive sensitivity, the advanced system features of

the SX1239 include a 66 byte RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and

configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU

requirements.

The SX1239 complies with both ETSI and FCC regulatory requirements and is available in a 5 x 5 mm QFN 24 lead

package

1.1. Simplified Block Diagram

VBAT1&2

VR_ANA

VR_DIG

Power Distribution System

RC

Oscillator

RFIN

LNA

Single to

Differential

Mixers

Σ/Δ

Modulators

RESET

SPI

RSSI

AFC

GND

Division by

2, 4 or 6

Tank

Inductor

Loop

Frac-N PLL

NC

Filter

Synthesizer

NC

NC

XO

32 MHz

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

Frequency Synthesis

Receiver Blocks

XTAL

GND

Control Blocks

Primarily Analog

Primarily Digital

Figure 1. Block Diagram

Rev 3 - Jan 2011

Page 8

www.semtech.com

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