SAA9750H View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
SAA9750H Datasheet PDF : 24 Pages
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Philips Semiconductors
Camera Digital Signal Processor
(CAMDSP)
Preliminary specification
SAA9750H
Data input/output timing (CLK1 and CLK2)
VDD = 2.7 to 3.3 V; VIL = 0 V; VIH = VDD; Vref = 0.5VDD;Tamb = −20 to +70 °C; tr and tf = 6 ns; output load
capacitance = 20 pF; unless otherwise specified.
SYMBOL
tDIs
tDIh
tDOd
tDOh
tduty
PARAMETER
data input set-up time
data input hold time
data output delay time
data output hold time
duty factor of CLK1 and CLK2
CONDITIONS
note 1
note 1
notes 2 and 3
notes 2 and 3
MIN.
5
8
−
−
−
TYP.
−
−
−
−
50
MAX.
−
−
50
50
−
Notes
1. Data inputs: SYNCI, CPOB, CDS0 to CDS8, VRST, HRST, R, G, B, TSW, YENC0 to YENC7, LSW and
UVENC0 to UVENC7.
2. Data outputs: UVSEL, UV0 to UV7, Y0 to Y7, WCLIP, CSYNC, HSYNC, FLD, HD, VD and CP2.
3. Tamb = +25 °C; VDD = 3.0 V.
UNIT
ns
ns
ns
ns
%
CLK1 and
CLK2
data inputs
data outputs
tf
90%
Vref
10%
tDOd
90%
10%
tDIs
90%
10%
tDIh
90%
10%
tDOh
90%
10%
tr
90% VIH
10%
VIL
VIH
VIL
VOH
VOL
MHA306
1996 Feb 16
Fig.4 Data input/output timing (CLK1 and CLK2).
10
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