T2801
3-Wire Bus Protocol Timing Diagram
DATA
CLOCK
ENABLE
TL
TPER
Figure 4.
TC
TS TH
Description
Clock period
Set time data to clock
Hold time data to clock
Clock pulse width
Set time enable to clock
Hold time enable to data
Time between two protocols
Symbol
TPER
TS
TH
TC
TL
TEC
TT
Min. Value
125
60
60
60
200
0
250
TEC TT
16525
Unit
ns
ns
ns
ns
ns
ns
ns
TX DATA Timing
RefCLK
TX_DATA
TS TH
Set-up time TX DATA
TS
Hold time TX DATA
TH
Figure 5. TX DATA timing
10 ns
10 ns
Absolute Maximum Ratings
All voltages refer to GND
Parameter
Supply voltage regulator Pin 10
Supply voltage
Pins 7, 12, 14, 33 and 42
Logic input voltage
Pins 1, 2, 3, 38, 39, 44,
45, 46, 47 and 48
Junction temperature
Storage temperature
Thermal Resistance
Parameter
Junction ambient
TS and TH must be considered for both (falling and
rising) edges of RefCLK when using REF_CLK =
10.368 MHz.
Symbol
Min.
Max.
Unit
VS_REG
3.2
4.7
V
VS
3.0
4.7
V
VIN
– 0.3
VS
V
Tjmax
150
_C
Tstg
–40
150
_C
Symbol
RthJA
Value
t.b.d.
Unit
K/W
20 (27)
Preliminary Information
Rev. A9, 11-Dec-01