DS2181A View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated

Part Name

Description

Manufacturer

DS2181A

CEPT Primary Rate Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2181A

PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 3

PIN SYMBOL TYPE

DESCRIPTION

14

INT

O Receive Alarm Interrupt. Flags host controller during alarm

conditions. Active low; open drain output.

15

SDI

I

Serial Data In. Data for on-chip control registers; sampled on rising

edge of SCLK.

16

SDO

O Serial Data Out. Control and status data from on-chip registers.

Updated on falling edge of SCLK; tri-stated during port write or when

CS is high.

17

CS

I

Chip Select. Must be low to write or read the serial port.

18

SCLK

I

Serial Data Clock. Used to write or read the serial port registers.

19

SPS

I

Serial Port Select. Tie to VDD to select the serial port. Tie to VSS to

select the hardware mode.

POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 4

PIN SYMBOL TYPE

DESCRIPTION

20

VSS

32

TEST

-

Signal Ground. 0.0 volts.

I

Test Mode. Tie to VSS to select the old DS2181 sync algorithm and to

tri–state the synchronizer status pins on the DS2181AQ. Tie to VDD

to select the new DS2181A sync algorithm and activate the

synchronizer status pins on the DS2181AQ.

40

VDD

-

Positive Supply. 5.0 volts.

5 of 32

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