MC7660 View Datasheet(PDF) - ON Semiconductor
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MC7660 Datasheet PDF : 10 Pages
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MC7660
Simple Negative Voltage Converter
Figure 4 shows typical connections to provide a negative
supply where a positive supply is available. A similar
scheme may be employed for supply voltages anywhere in
the operating range of +1.5 V to +10 V, keeping in mind that
pin 6 (LV) is tied to the supply negative (GND) only for
supply voltages below 3.5 V.
The output characteristics of the circuit in Figure 4 are
those of a nearly ideal voltage source in series with 70 W.
Thus, for a load current of -10 mA and a supply voltage of
+5.0 V, the output voltage would be -4.3 V.
The dynamic output impedance of the MC7660 is due,
primarily, to capacitive reactance of the charge transfer
capacitor (C1). Since this capacitor is connected to the output
for only 1/2 of the cycle, the equation is:
XC
+
2
2pf C1
+
3.18W,
where f = 10kHz and C1 = 10µF.
V+
1
8
2
7
MC7660
C1
3
6
4
5
C1
C1 +
10 mF
V+
1
8
2
7
MC7660
3
6
4
5
VOUT
C2
+ 10 mF
Figure 4. Simple Negative Converter
Parallel Devices
Any number of MC7660 voltage converters may be
paralleled to reduce output resistance (Figure 5). The
reservoir capacitor, C2, serves all devices, while each device
requires its own pump capacitor, C1. The resultant output
resistance would be approximately:
ROUT
+
ROUT (of MC7660)
n (number of devices)
1
8
2
7
RL
MC7660
3
6
4
5
+ C2
Figure 5. Paralleling Devices Lowers Output Impedance
Cascading Devices
The MC7660 may be cascaded as shown (Figure 6) to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
VOUT = -n (VIN)
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual MC7660
ROUT values.
Changing the MC7660 Oscillator Frequency
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 7. In order to prevent
possible device latch-up, a 1.0 kW resistor must be used in
series with the clock output. In a situation where the designer
has generated the external clock frequency using TTL logic,
the addition of a 10 kW pull-up resistor to V+ supply is
required. Note that the pump frequency with external
clocking, as with internal clocking, will be 1/2 of the clock
frequency. Output transitions occur on the positive-going
edge of the clock.
It is also possible to increase the conversion efficiency of
the MC7660 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is
achieved by connecting an additional capacitor, COSC, as
shown in Figure 8. Lowering the oscillator frequency will
cause an undesirable increase in the impedance of the pump
(C1) and the reservoir (C2) capacitors. To overcome this,
increase the values of C1 and C2 by the same factor that the
frequency has been reduced. For example, the addition of a
100 pF capacitor between pin 7 (OSC) and pin 8 (V+) will
lower the oscillator frequency to 1.0 kHz from its nominal
frequency of 10 kHz (a multiple of 10), and necessitate a
corresponding increase in the values of C1 and C2 (from
10 µF to 100 µF).
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