TC7129 View Datasheet(PDF) - TelCom Semiconductor Inc => Microchip

Part Name

Description

Manufacturer

TC7129

4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS

TelCom Semiconductor Inc => Microchip 

4-1/2 DIGIT ANALOG-TO-DIGITAL

CONVERTER WITH ON-CHIP LCD DRIVERS

TC7129

TC7129

DP4/OR, PIN 20

DP3/UR, PIN 21

LATCH/HOLD PIN 22

CONTINUITY, PIN 27

Ϸ500 kΩ

Figure 15. Input/Output Pin Schematic

Common and Digital Ground

The common and digital ground (DGND) outputs are

generated from internal zener diodes. The voltage between

V+ and DGND is the internal supply voltage for the digital

section of the TC7129. Common can source approximately

12 µA; DGND has essentially no source capability.

Low Battery

The low battery annunciator turns on when supply

voltage between V+ and V– drops below 6.8V. The internal

zener has a threshold of 6.3V. When the supply voltage

drops below 6.8V, the transistor tied to V– turns OFF, pulling

the "Low Battery" point HIGH. (See Figure 16.)

12 µA

–

N

+

24 V+

3.2V

COM

28

5V

LOGIC

SECTION

TC7129

36 DGND

P

N

23 V–

Figure 16. Digital Ground (DGND) and Common Outputs

Sequence and Results Counter

A sequence counter and associated control logic pro-

vide signals that operate the analog switches in the integra-

tor section. The comparator output from the integrator gates

the results counter. The results counter is a six-section up/

down decade counter which holds the intermediate results

from each successive integration.

Overrange and Underrange Outputs

When the results counter holds a value greater than

±19,999, the DP4/OR output (pin 20) is driven HIGH. When

the results counter value is less than ±1000, the DP3/UR

output (pin 21) is driven HIGH. Both signals are valid on the

falling edge of LATCH/HOLD (L/H) and do not change until

the end of the next conversion cycle. The signals are

updated at the end of each conversion unless the L/H input

(pin 22) is held HIGH. Pins 20 and 21 can also be used as

inputs for external control of decimal points 3 and 4. Figure

15 shows a schematic of the input/output nature of these

pins.

Latch/Hold

The L/H output goes LOW during the last 100 cycles of

each conversion. This pulse latches the conversion data into

the display driver section of the TC7129. This pin can also

be used as an input. When driven HIGH, the display will not

be updated; the previous reading is displayed. When driven

LOW, the display reading is not latched; the sequence

counter reading will be displayed. Since the counter is

counting much faster than the backplanes are being up-

dated, the reading shown in this mode is somewhat erratic.

Display Driver

The TC7129 drives a triplexed LCD with three back-

planes. The LCD can include decimal points, polarity sign,

and annunciators for continuity and low battery. Figure 17

shows the assignment of the display segments to the

backplanes and segment drive lines. The backplane drive

frequency is obtained by dividing the oscillator frequency by

1200. This results in a backplane drive frequency of 100 Hz

for 60 Hz operation (120 kHz crystal) and 83.3 Hz for 50 Hz

operation (100 kHz crystal).

Backplane waveforms are shown in Figure 18. These

appear on outputs BP1, BP2, BP3 (pins 16, 17, and 18). They

remain the same regardless of the segments being driven.

Other display output lines (pins 4 through 15) have

waveforms that vary depending on the displayed values.

Figure 19 shows a set of waveforms for the A, G, D outputs

(pins 5, 8, 11, and 14) for several combinations of "ON"

segments.

3-244

TELCOM SEMICONDUCTOR, INC.

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