TC7107ACKW View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
TC7107ACKW Datasheet PDF : 34 Pages
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TC7106/A/TC7107/A
3.0 DETAILED DESCRIPTION
(All Pin designations refer to 40-Pin PDIP.)
3.1 Dual Slope Conversion Principles
The TC7106A and TC7107A are dual slope, integrating
Analog-to-Digital Converters. An understanding of the
dual slope conversion technique will aid in following the
detailed operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
• Input Signal Integration
• Reference Voltage Integration (De-integration)
The input signal being converted is integrated for a
fixed time period (TSI). Time is measured by counting
clock pulses. An opposite polarity constant reference
voltage is then integrated until the integrator output
voltage returns to zero. The reference integration time
is directly proportional to the input signal (TRI). See
Figure 3-1.
Analog
Input
Signal
C
Integrator
–
+
Comparator
–
+
+/–
REF
Voltage
Switch
Driver
Phase
Control
Polarity Control
Control
Logic
DISPLAY
VIN µ VREF
VIN µ1/2 VREF
Fixed Variable
Signal Reference
Integrate Integrate
Time Time
Counter
FIGURE 3-1:
Basic Dual Slope Converter.
In a simple dual slope converter, a complete
conversion requires the integrator output to “ramp-up”
and “ramp-down.” A simple mathematical equation
relates the input signal, reference voltage and
integration time.
EQUATION 3-1:
Where:
∫ ---1----
RC
TSI
VIN(t)dt
0
=
V----R----T---R---I
RC
VR = Reference voltage
TSI = Signal integration time (fixed)
TRI = Reference voltage integration time
(variable).
For a constant VIN:
EQUATION 3-2:
VIN = VR
TRI
TSI
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated or averaged to zero during the integration
periods. Integrating ADCs are immune to the large
conversion errors that plague successive
approximation converters in high noise environments.
Interfering signals with frequency components at
multiples of the averaging period will be attenuated.
Integrating ADCs commonly operate with the signal
integration period set to a multiple of the 50/60Hz
power line period (see Figure 3-2).
30
20
10
0
0.1/T
T = Measured Period
1/T
Input Frequency
10/T
FIGURE 3-2:
Normal Mode Rejection of
Dual Slope Converter.
Where:
FOSC
VFS
RINT
VINT
CINT
=
(---4---0---0---0---)---⎝⎛---F-------O----1----S------C----⎠⎞---⎝⎛---R---V-----I---F-N-----S--T----⎠⎞-
VINT
= Clock Frequency at Pin 38
= Full Scale Input Voltage
= Integrating Resistor
= Desired Full Scale Integrator Output
Swing
DS21455D-page 8
© 2008 Microchip Technology Inc.
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