M80C186 View Datasheet(PDF) - Intel
Part Name
Description
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M80C186 Datasheet PDF : 59 Pages
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M80C186
Poll and Poll Status Registers
These registers contain polling information The for-
mat of these registers is shown in Figure 32 They
can only be read Reading the Poll register consti-
tutes a software poll This will set the IS bit of the
highest priority pending interrupt Reading the poll
status register will not set the IS bit of the highest
priority pending interrupt only the status of pending
interrupts will be provided
Encoding of the Poll and Poll Status register bits are
as follows
Sx
Encoded information that indicates the
vector type of the highest priority inter-
rupting source Valid only when INTREQ
e1
INTREQ This bit determines if an interrupt request
is present Interrupt Request e 1 no In-
terrupt Request e 0
SLAVE MODE OPERATION
When slave mode is used the internal M80C186 in-
terrupt controller will be used as a slave controller to
an external master interrupt controller The internal
M80C186 resources will be monitored by the internal
interrupt controller while the external controller
functions as the system master interrupt controller
Upon reset the M80C186 will be in master mode To
provide for slave mode operation bit 14 of the relo-
cation register should be set
Because of pin limitations caused by the need to
interface to an external M82C59A master the inter-
nal interrupt controller will no longer accept external
inputs There are however enough M80C186 inter-
rupt controller inputs (internally) to dedicate one to
each timer In this mode each timer interrupt source
has its own mask bit IS bit and control word
In slave mode each peripheral must be assigned a
unique priority to ensure proper interrupt controller
operation Therefore it is the programmer’s respon-
sibility to assign correct priorities and initialize inter-
rupt control registers before enabling interrupts
Slave Mode External Interface
The configuration of the M80C186 with respect to an
external M82C59A master is shown in Figure 33
The INT0 (Pin 45) input is used as the M80C186
CPU interrupt input INT3 (Pin 41) functions as an
output to send the M80C186 slave-interrupt-request
to one of the 8 master-PIC-inputs
15 14 13
5
4
3
2
1
0
SPEC
NSPEC
0
0
0 S4 S3 S2 S1 S0
Figure 31 EOI Register Format
15 14 13
5
4
3
2
1
0
INT
REQ
0
0
0 S4 S3 S2 S1 S0
Figure 32 Poll and Poll Status Register Format
37
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