TDA2579C View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TDA2579C

Synchronization circuit with synchronized vertical divider system for 60 Hz

Philips Electronics 

Philips Semiconductors

Synchronization circuit with synchronized

vertical divider system for 60 Hz

Preliminary specification

TDA2579C

The maximum allowed starting current is 9.7 mA

(Tamb = 25 °C).

The main supply should be connected to pin 10 and pin 9

should be used for ground. When the voltage on pin 10

increases from zero to its final value (typ. 12 V) a part of

the supply current of the starting circuit is taken from pin 10

via internal diodes and the voltage on pin 16 will stabilize

on a typical value of 9.3 V. In stabilized conditions

(V10 > 10 V) the minimum required supply current into

pin 16 is approximately 2.5 mA.

All other IC functions are switched on via the main supply

voltage on pin 10. When this voltage reaches a value of

approximately 7 V the horizontal phase detector is

activated and the vertical ramp on pin 3 is started. The

second phase detector circuit and burst pulse circuit are

started when the voltage on pin 10 reaches the stabilized

voltage value of pin 16 typical 9.3 V.

To close the second phase detector loop a flyback pulse

must be applied to pin 12. When no flyback pulse is

detected the duty factor of the horizontal output stage

is 50%.

For remote switch-off pin 16 can be connected to ground

(via a npn transistor with a collector series resistor of

approximately 500 Ω) which decreases pin 16 voltage to

≤5 V and switches off the horizontal output pulse.

Horizontal oscillator, horizontal output transistor and

second phase detector

The horizontal oscillator is connected to pin 15. The

frequency is set by an external RC combination between

pin 15 and ground (pin 9). The open collector horizontal

output stage is connected to pin 11. An internal Zener

diode configuration limits the open voltage of pin 11 to

approximately 14.5 V. The horizontal output transistor at

pin 11 is blocked until the current into pin 16 reaches a

value of approximately 5 mA.

A higher current results in a horizontal output signal at

pin 11, which starts with a duty factor of approximately

40% HIGH.

The duty factor is set by an internal current-source-loaded

npn emitter follower stage connected to pin 14 during

starting. When pin 16 changes over to voltage stabilization

the npn emitter follower and current source load at pin 14

are switched off and the second phase detector is

activated, provided a horizontal flyback pulse is present at

pin 12. When no flyback pulse is detected at pin 12 the

duty factor of the horizontal output stage is set to 50%. The

phase detector circuit at pin 14 compensates for storage

time in the horizontal deflection output state.

The horizontal output pulse duration is 29 µs HIGH for

storage times between 1 µs and 17 µs (flyback pulse of

12 to 29 µs). A higher storage time increases the

HIGH time.

Horizontal picture shift is possible by forcing an external

charge or discharge current into the capacitor at pin 14.

Mute output and 60 Hz identification (pin 13)

The collector of an npn transistor is connected to pin 13.

When the voltage on pin 18 drops below 1.2 V (no TV

transmitter) the npn transistor is switched on. When the

voltage on pin 18 increases to a level of approximately

1.8 V (new TV transmitter found) the npn transistor is

switched off.

This function is available when pin 13 is connected to

pin 10 (+12 V) via an external pull-up resistor of 10 to

20 kΩ. When no TV transmitter is identified the voltage on

pin 13 will be LOW (<0.5 V).

When an M-system TV transmitter with a divider ratio <576

(60 Hz) is found an internal pnp transistor with its emitter

connected to pin 13 will force the output voltage down to

approximately 7.6 V.

Sandcastle output (pin 17)

The sandcastle output pulse generated at pin 17 has three

different voltage levels. The highest level (10.4 V) can be

used for burst gating and black level clamping. The second

level (4.5 V) is obtained from the horizontal flyback pulse

at pin 12 and is used for horizontal blanking. The third level

(2.5 V) is used for vertical blanking and is derived via the

vertical divider system. For 60 Hz the blanking pulse

duration is 34 clock pulses started from the reset of the

vertical divider system.

For TV signals which have a divider ratio between 522 and

528 the vertical blanking pulse is started at the first

equalizing pulse.

January 1994

10

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