TDA2579C View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TDA2579C

Synchronization circuit with synchronized vertical divider system for 60 Hz

Philips Electronics 

Philips Semiconductors

Synchronization circuit with synchronized

vertical divider system for 60 Hz

Preliminary specification

TDA2579C

Vertical sawtooth

To generate a vertical linear sawtooth voltage a capacitor

should be connected to pin 3. The recommended value is

150 nF to 330 nF. The capacitor is charged via an internal

current source starting at the reset of the divider system.

The voltage on the capacitor is monitored by a comparator

which is also activated at reset. When the capacitor has

reached a voltage value of 5.0 V the voltage is kept

constant until the charging period ends. The charging

period width is 26 clock pulses. At clock pulse 26 the

comparator is switched off and the capacitor is discharged

by an npn transistor current source the value of which can

be set by an external resistor connected between pin 4

and ground (pin 9). Pin 4 is connected to a pnp transistor

current source which determines the current of the npn

current source at pin 3. The pnp current source on pin 4 is

connected to an internal Zener diode reference voltage

which has a typical voltage of 7.5 V. The recommended

operating current range is 10 to 75 µA. The resistor at

pin 4 should be 100 to 770 kΩ. By using a double current

mirror concept the vertical sawtooth pre-correction voltage

can be set to the required value by external components

connected between pins 3 and 4 or by superimposing a

correction voltage in series with the earth connection of the

resistor connected to pin 4.

The vertical amplitude is set by the current of pin 4.

Vertical feedback

The vertical feedback voltage of the output stage has to be

applied to pin 2. For the normal amplitude adjustment the

values are DC = 1 V and AC = 0.8 V (p-p).

The low DC voltage value improves the picture bounce

behaviour as less parabola compensation is required.

Even a DC-coupled feedback circuit is possible.

Vertical guard

The IC also contains a vertical guard circuit. This circuit

monitors the vertical feedback signal on pin 2. When the

level on pin 2 is below 0.35 V or higher than 1.85 V the

guard circuit inserts a continuous voltage level of 2.5 V in

the sandcastle output signal of pin 17. This results in

blanking of the picture displayed, thus preventing a

burnt-in horizontal line.

Vertical driver output

The driver output is at pin 1, it can deliver a drive current

of 1.5 mA at 5 V output. The internal impedance is

approximately 170 Ω. The output pin is also connected to

an internal current source with a sink current of 0.25 mA.

Integration time of the vertical synchronization pulse

separator

The vertical sync separator has two integration times:

• long time; typical 19 µs, valid for 1.8 ≤ V18 ≤ 7.8 V

(no noise detected)

• short time; typical 12 µs, valid for noise detected and

V18 ≥ 1.2 V.

When V18 drops below 1.2 V, the integration time is forced

back to 19 µs to prevent switching of the divider system to

the wide window mode for noise only conditions.

Sync separator, phase detector and TV-station

identification (pins 5, 6, 7 and 18)

SYNC SEPARATOR

The video input signal is connected to pin 5. The sync

separator is designed such that the slicing level is

independent of the amplitude of the sync pulse. The black

level is measured and stored in the capacitor at pin 7. The

slicing level is stored in the capacitor at pin 6. The slicing

level value can be chosen by the value of the external

resistor connected between pins 6 and 7. The value is

given by the formula:

p = -5---.-3---R--×--S---R-----S- × 100 (RS value in kΩ) .

Where RS is the resistor connected between pins 6 and 7

and the top sync levels equals 100%. The recommended

resistor value is 5.6 kΩ.

BLACK LEVEL DETECTOR

A gating signal is used for the black level detector. This

signal is composed of an internal horizontal reference

pulse with a duty factor of 50% and the flyback pulse at

pin 12. In this way the TV transmitter identification

operates also for all DC conditions at input pin 5 (no video

modulation, plain carrier only).

During the vertical blanking interval the slicing detector is

inhibited by a signal which starts with the anti-top-flutter

pulse and ends with the reset of the vertical divider circuit.

In this way shift of the slicing level due to the vertical sync

signal is reduced and separation of the vertical sync pulse

is improved.

An internal noise inverter is activated when the video level

at pin 5 decreases below 0.7 V.

January 1994

7

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