TDA7333NTR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TDA7333NTR

RDS/RBDS processor

STMicroelectronics 

Functional description

TDA7333N

Figure 7. RAM buffer usage

INTERNAL REGISTERS

rds_int[7..0]

rds_qu[7..0] rds_corrp[7..0] rds_bd_h[7..0] rds_bd_l[7..0] rds_bd_ctrl[7..0] sinc4reg[7..0]

testreg[7..0]

pllreg4[7..0]

write access

(external)

RAM BUFFER

(24 blocks)

pllreg0[7..0]

read access

(internal)

SA_DATAOUT

(spi mode)

SDA_DATAIN

(i2c mode)

rds_int[7..0]

I2C/SPI SHIFT REGISTER

rds_qu[7..0] rds_corrp[7..0] rds_bd_h[7..0] rds_bd_l[7..0] rds_bd_ctrl[7..0] sinc4reg[7..0]

testreg[7..0]

pllreg4[7..0]

pllreg0[7..0]

After power up, or after resynchronization by setting “ar_res” rds_int[5] to one, incoming

RDS blocks are stored in the RAM buffer when synchronization has been established

(Figure 8). But if the bit “syncw” rds_bd_ctrl[0] (refer to Section 3.8.6) is cleared, every

received RDS block is stored, also without synchronization. This means if the RDS is not

synchronized, every received consecutive 26 RDS data bits are treated as a RDS block.

Figure 8. RAM buffer update depends on “syncw” bit rds_bd_ctrl[0]

Synchro-

nization flag 1

"synch"

0

Write to RAM

Buffer if

"syncw" = 1

Write to RAM

Buffer if

"syncw" = 0

RDS data

bits

Block A

Block B

time

time

time

Block C

time

The RAM buffer is used as a circular FIFO (Figure 9). If more than 24 blocks are written, the

oldest data will be overwritten. One level of the buffer consists of 4 bytes (2 information

bytes, 2 RDS data bytes). If less than 4 bytes of the RAM buffer are read out from the

master via the SPI or I2C interface, the buffer address will not be incremented.

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