Philips Semiconductors
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
Preliminary specification
TDA9952
SYMBOL
PARAMETER
CONDITIONS
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
Vreset(max)
Ii(IN)
Ci
tCDS(min)
th(IN;SHP)
th(IN;SHD)
maximum CDS input
voltage (peak-to-peak
value)
VCC = 2.85 V
VCC ≥ 3.0 V
maximum CDS input reset
pulse
input current into pin IN at floating gate level
input capacitance
CDS control pulses
minimum active time
Vi(CDS)(p-p) = 800 mV;
black-to-white transition in
1 pixel with 98.5% Vi
recovery
CDS input hold time
(pin IN) compared to
control pulse SHP
Figs 3 and 4
CDS input hold time
(pin IN) compared to
control pulse SHD
Figs 3 and 4
Programmable Gain Amplifier (PGA)
DRPGA
∆GPGA
PGA dynamic range
PGA gain step
ADC
DNL
differential non linearity ramp input
ADCres
ADC resolution
Total chain characteristics (CDS + PGA + ADC)
fpix(max)
fpix(min)
OCCD(max)
maximum pixel rate
minimum pixel rate
maximum offset voltage
between CCD floating
level and CCD dark pixel
level
OCCD(max) = ±100 mV
OCCD(max) = ±200 mV
tCLKH
tCLKL
td(SHD;CLK)
CLK pulse width HIGH
CLK pulse width LOW
time delay between
SHD and CLK
Figs 3 and 4
tsu(BLK;SHD) set-up time of BLK
compared to SHD
Figs 3 and 4
Vi(IN)
video input voltage for
ADC full-scale output
PGA code = 00
PGA code = 383
MIN.
650
800
−
−
−
11
3
3
−
0.08
−
−
25
−
−
−200
15
15
−
5
−
−
TYP.
−
−
−
−
2
−
−
−
36
0.10
±0.5
10
−
−
−
−
−
−
10
−
800
12.7
MAX. UNIT
−
mV
−
mV
1.5
V
3
µA
−
pF
−
ns
−
ns
−
ns
−
dB
0.12 dB
±0.9 LSB
−
bits
−
1
2
+200
MHz
MHz
MHz
mV
−
ns
−
ns
−
ns
−
ns
−
mV
−
mV
2002 Aug 21
9