TDA9965AHL View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
TDA9965AHL Datasheet PDF : 22 Pages
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Philips Semiconductors
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
Product specification
TDA9965A
Table 1 Serial interface programming
ADDRESS BITS
A1
A0
0
0
0
1
1
0
1
1
SDATA BITS SD0 to SD9
clamp reference of ADC (SD0 to SD9); note 1
cut-off frequency of CTH (SD0 to SD3)
PGA gain control (SD0 to SD9)
edge control for pulses SHP, SHD, CLPOB, CLPADC and CLKADC (note 2):
SD0 = 1, SHP and SHD sample on LOW level
SD1 = 1, CLPADC and CLPOB activated on HIGH level
SD2 = 1, CLKADC activated with rising edge
Notes
1. PGA gain register must always be refreshed after clamp code register content has been changed.
2. When pin CLPADC = HIGH (SD1 = 1; serial interface), the ADC input is clamped to the voltage level of Vref. Pin Vref
is connected to ground via a capacitor.
When the power supplies increase from zero to VCC, the init-on-power block initializes the circuit as follows:
• Cut-off frequency of the CTH circuit is set to: code fco(CTH) = 0
• PGA gain control is set to: code GPGA = 0
• Clamp code of the ADC is set to: code ADCCLP = 0
• SHP and SHD sample on HIGH level; CLKADC activated with rising edge
• CLPOB and CLPADC activated on HIGH level.
Table 2 Standby selection
PIN STDBY
HIGH
LOW
DATA BITS SD9 to SD0
logic 0
active
ICCA + ICCD
4 mA (typical); note 1
84 mA (typical)
Note
1. If an external regulator is used it has to be switched off in standby mode in order to avoid extra power consumption
by the TDA9965A.
2004 Jul 05
11
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