Philips Semiconductors
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
Product specification
TDA9965A
SYMBOL
PARAMETER
CONDITIONS
MIN.
tW(SHD)
SHD pulse width
Vi(IN) = 1000 mV;
8
transition (98.5%) in 1 pixel;
code fco(CTH) = 0000;
see Fig.5
code fco(CTH)
0000
−
0001
−
0010
−
0100
−
1000
−
1111
−
th(IN-SHP)
CTH input hold time
see Fig.5
−
compared to control pulse
SHP
th(IN-SHD)
CTH input hold time
see Fig.5
−
compared to control pulse
SHD
Programmable Gain Amplifier (PGA) output: pin PGAOUT
VPGAOUT(p-p) PGA output amplifier
−
dynamic voltage level
(peak-to-peak value)
VPGAOUT(b) PGA output amplifier black code C(CLP) = 0
−
level voltage
ZPGAOUT
PGA output amplifier
output impedance
fpix at 10 kHz for minimum −
and maximum values
IPGAOUT
PGA output current drive static
−
GPGA(min)
minimum gain of PGA
code GPGA = 0
−
circuit
GPGA(max)
maximum gain of PGA
code GPGA ≥767
−
circuit
Analog-to-Digital Converter (ADC)
fpix(max)
tW(CLKADC)H
tW(CLKADC)L
SRCLKADC
Vi(ADCIN)(p-p)
maximum pixel frequency
CLKADC pulse width
HIGH
CLKADC pulse width
LOW
CLKADC input slew rate
ADC input voltage
(peak-to-peak value)
40
Vi(IN) = 1000 mV;
11
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
Vi(IN) = 1000 mV;
11
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128
rising and falling edges;
0.5
10% to 90%
with internal regulator
−
TYP.
−
7
12
16
22
32
49
3
3
2 000
1.475
5
−
0
36
−
−
−
−
2
MAX.
−
−
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
mV
V
Ω
mA
dB
dB
MHz
ns
ns
V/ns
V
2004 Jul 05
8