TDA9965AHL View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
TDA9965AHL Datasheet PDF : 22 Pages
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Philips Semiconductors
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras
Product specification
TDA9965A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
Ii(ADCIN)
VRB
ADC input current
ADC reference voltage
bottom
−2
−
−
1.30
VRT
DNL
td(s)
ADC reference voltage top
−
differential non-linearity ramp input; fpix = 30 MHz −
sampling delay
see Fig.5
−
3.65
±0.5
−
Total chain characteristics (CTH + PGA + ADC)
td(SHD-CLKADC)
th(SHD-CLKADC)
Ntot(rms)
OCCD(max)
delay between
SHD and CLKADC
SHD hold time compared
to CLKADC
total noise from CTH input
to ADC output
(RMS value)
maximum offset voltage
between CCD floating
level and CCD dark pixel
level
Vi(IN) = 1000 mV;
transition (95%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
Vi(IN) = 32 mV;
transition (95%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
GPGA = 0 dB;
code fco(CTH) = 0000
GPGA = 30 dB;
code fco(CTH) = 0000; note 1
see Fig.11
−
−
−
−
−200
15
0
0.85
6
−
Vn(i)(eq)(rms) equivalent input noise
GPGA = 30 dB;
−
90
(RMS value)
code fco(CTH) = 0000; note 1
Digital outputs (fpix = 40 MHz; CL = 10 pF)
VOH
HIGH-level output voltage IOH = −1 mA
VOL
LOW-level output voltage IOL = 1 mA
th(o)
output hold time
see Fig.5
td(o)
output delay
VCCO = 5.25 V
VCCO = 3 V
VCCO − 0.5 −
0
−
10
−
−
20
−
26
Serial interface
fSCLK(max)
maximum clock frequency
of serial interface
5
−
Note
1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.
MAX.
+120
−
−
±0.9
5
−
−
−
−
+200
−
VCCO
0.5
−
25
31
−
UNIT
µA
V
V
LSB
ns
ns
ns
LSB
LSB
mV
µV
V
V
ns
ns
ns
MHz
2004 Jul 05
9
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