SM8702AM
AC Electrical Characteristics
CPU clock characteristics 1
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VDDL = 2.5V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless other-
wise noted.
Parameter
Output clock rise time1
Output clock fall time1
Duty cycle
Output clock jitter1
Output clock skew 1
Symbol
Condition
Rating
Unit
min
typ
max
tr
VOL = 0.4V → VOH = 2.0V transition time
–
tf
VOH = 2.0V → VOL = 0.4V transition time
–
Dt VT = 1.25V
45
tjc V T = 1.25V, rising edge Cycle-to-cycle jitter
–
ts k w
V T = 1.25V, rising edge
Between CPUCLK0 and
CPUCLK1
–
–
2.0
ns
–
2.0
ns
50
55
%
–
250
ps
–
250
ps
Clock frequency stabilize time1
Output impedance2
tstb Cold start
ZO
VO = 0.5VDDL
Supply ON (VDD = 3.3V)
until clock reaches
–
–
3
ms
specified frequency
10
–
90
Ω
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
CPU clock characteristics 2
Ta = 0 to 70°C, VDD = VDDL = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless otherwise noted.
Parameter
Output clock rise time1
Output clock fall time1
Duty cycle
Output clock jitter1
Output clock skew 1
Symbol
Condition
Rating
Unit
min
typ
max
tr
VOL = 0.4V → VOH = 2.4V transition time
–
tf
VOH = 2.4V → VOL = 0.4V transition time
–
Dt VT = 1.5V
45
tjc V T = 1.5V, rising edge Cycle-to-cycle jitter
–
ts k w
V T = 1.5V, rising edge
Between CPUCLK0 and
CPUCLK1
–
–
2.5
ns
–
2.5
ns
50
55
%
–
250
ps
–
250
ps
Clock frequency stabilize time1
Output impedance2
tstb Cold start
ZO
VO = 0.5VDDL
Supply ON (VDD = 3.3V)
until clock reaches
–
–
3
ms
specified frequency
10
–
60
Ω
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—7