XRD87L94 View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRD87L94

CMOS, 1 MSPS, 12-Bit Analog-to-Digital Converter with Parallel Logic Interface Port

Exar Corporation 

XRD87L94

OVERVIEW OF THE XRD87L94 PINS & OPERATION

NOTES

OE: Output Enable (Input)

This signal controls the 3-state drivers on the digital outputs

DB0 - DB11 as shown in Figure 2. During normal operation, OE

should be held low so that all outputs are enabled (NOTE: an in-

ternal resistor will pull OE to this level if it is not connected).

When OE is driven high, DB0 - DB11 goes into high impedance

mode. This control operates asynchronously to the clock and

only controls the output drivers. The internal output register will

get updated if the clock is running while the outputs are in 3-state

mode. The aperture and OE signals are internally combined to

enable the output data. If aperture is high, the output data bits

are tri-stated, independent of OE. Figure 3. shows the circuit

used to tri-state the output. This will reduce the errors introduced

by digital output coupling during the AIN sample time.

MINV

DQ

latch

EN

CLK

DQ

latch

EN

DB11

3-state

driver

Figure 4. MINV Simplified Logic Circuit

VIN Analog Input

This part has a switched capacitor type input circuit. This

means that the input impedance changes with the phase of the

input clock. VIN is sampled at the high to low clock transition.

The diagram Figure 5. shows an equivalent input circuit.

APERTURE: Aperture Delay Sync (Output)

This signal is high when the internal sample/hold function is

sampling VIN, and goes low when it is in the hold mode (when the

ADC is comparing the stored input value to the reference lad-

der). The value of VIN at the high to low transition of APERTURE

is the value that will be digitized. A system can monitor this sig-

nal and adjust the CLK to accurately synchronize the sampling

point to an external event. The aperture and OE signals are in-

ternally combined to enable the output data. If aperture is high,

the output data bits are tri-stated, independent of OE. This will

reduce the errors introduced by digital output coupling during

the AIN sample time.

MINV: Digital Output Format (Input)

This signal controls the format of the digital output data bits

DB0 – DB11. Normally it is held low so the data is in straight

binary format (all 0’s when VIN = VRB; all 1’s when VIN = VRT). If

MINV is pulled high then the MSB (DB11) will be inverted.

MINV is meant to be a static digital signal. If it is to change

during operation, it should only change when the CLK is low.

Changing MINV on the wrong phase of the CLK will not hurt any-

thing, but the effects on the digital outputs will not be seen until

the output latch of the output register is enabled. MINV has an

internal pull down device.

Rev. 1.00

AVDD

VIN

AGND

50Ω

CL

41pF 50Ω

8pF

CL

VRT + VRB +

1.5pF

CL

2

−

CL at PHASE = 1

Figure 5. Equivalent Input Circuit

R1, R2, R3: Reference Ladder Taps

These taps connect to every 1/4 point along the reference

ladder; R1 is 1/4th up from VRB, R3 is 3/4ths up from VRB (or

1/4th down from VRT). Normally these pins should have 0.1 mi-

crofarad capacitors to VSS; this helps reduce the INL errors by

stabilizing the reference ladder voltages.

These taps can also be used to alter the transfer curve of the

ADC. A 4-segment, piecewise linear, custom transfer curve can

be designed by connecting voltage sources to these pins.

This may be desirable to make the probability of codes for a

certain range of VIN be enhanced or minimized.

Sometimes this is referred to as probability density function

shaping, or histogram shaping.

The internal interconnect resistance from each of the tAP pins

to the ladder is less than 3Ω.

6

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