LH5P1632 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LH5P1632 Datasheet PDF : 10 Pages
| |||
LH5P1632
CMOS 512K (32K × 16) Pseudo-Static RAM
AC CHARACTERISTICS 1, 2, 3 (TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER
SYMBOL
–80 ns
MIN.
MAX.
–150 ns
MIN.
MAX.
UNIT
NOTE
READ OR WRITE CYCLE
Random read, write cycle time
tRC
140
210
ns
Read modify write cycle time
tRMW
205
280
ns
CE pulse width
tCE
80
10,000 150 10,000
ns
CE precharge time
tP
50
60
ns
Address setup time
tAS
0
0
ns
4
Address hold time
tAH
20
30
ns
4
Read command setup time
tRCS
0
0
ns
Read command hold time
tRCH
0
0
ns
CE access time
tCEA
80
150
ns
5
OE access time
tOEA
30
70
ns
5
CE to output in Low-Z
tCLZ
10
10
ns
OE to output in Low-Z
tOLZ
0
0
ns
OE setup time for WR
tOSW
0
0
ns
Output disable time from CE
tCHZ
0
25
0
35
ns
Output disable time from OE
tOHZ
0
25
0
35
ns
Output disable time from WR
tWHZ
0
25
0
35
ns
OE setup time
tOES
10
10
ns
OE hold time
tOEH
0
0
ns
OE lead time
tOEL
10
10
ns
Write command pulse width
tWCP
60
85
ns
Write command setup time
tWCS
60
85
ns
Write command hold time
tWCH
60
85
ns
Data setup time from WR
tDSW
30
50
ns
Data setup time from CE
tDSC
30
50
ns
Data hold time from WR
tDHW
0
0
ns
Data hold time from CE
tDHC
0
0
ns
Transition time (rise and fall)
tT
3
35
3
35
ns
Refresh time interval
tREF
4
4
ms
REFRESH CYCLE
Auto refresh cycle time
tFC
140
190
ns
Refresh delay time from CE
tRFD
50
60
ns
Refresh pulse width (Auto Refresh)
tFAP
30
8,000
80
8,000
ns
Refresh precharge time (Auto
Refresh)
tFP
40
30
ns
CE delay time from Refresh active
(Auto Refresh)
tFCE
160
225
ns
NOTES:
1. In order to initialize the circuit, CE and OEL/RFSH should be kept
VIH for 200 µs after power on and followed by at least 8 dummy
cycles.
2. AC characteristics shall be tested with tT = 5 ns.
3. AC characteristics are measured at the following condition (see figure
at right).
4. Address is latched at the negative edge of CE.
5. Measured with a load equivalent to 2TTL + 100 pF.
6. Data for the lower byte (I/O1 to I/O8) is latched at the positive edge
of LWR or the positive edge of CE. Data for the upper byte (I/O9 to
I/O16) is latched at the positive edge of UWR or the positive edge
of CE.
INPUT
OUTPUT
2.4 V
0.8 V
2.2 V
0.8 V
2.6 V
0.6 V
Figure 3. AC Characteristics
5P1632-9
4
Share Link: 