CDP1805AC View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
CDP1805AC Datasheet PDF : 30 Pages
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CDP1805AC, CDP1806AC
Static Electrical Specifications at TA = -40oC to +85oC, VDD ±5%, Except as Noted (Continued)
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
PARAMETER
VO
VIN
VDD
(NOTE 3)
(V)
(V)
(V)
MIN
TYP
MAX UNITS
Input Low Voltage (BUS0 - BUS7, ME), VIL
0.5, 4.5
-
5
-
-
1.5
V
Input High Voltage (BUS0 - BUS7, ME), VIH
0.5, 4.5
-
5
3.5
-
-
V
Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME)
Positive Trigger Threshold, VP
0.5, 4.5
-
5
2.2
2.9
3.6
V
Negative Trigger Threshold, VN
0.5, 4.5
-
5
0.9
1.9
2.8
V
Hysteresis, VH
0.5, 4.5
-
5
0.3
0.9
1.6
V
Input Leakage Current, IIN
-
0, 5
5
-
±0.1
±5
µA
Three-State Output Leakage Current, IOUT
0, 5
0, 5
5
-
±0.2
±5
µA
Input Capacitance, CIN
-
-
-
-
5
7.5
pF
Output Capacitance, COUT
-
-
-
-
10
15
pF
Total Power Dissipation (Note 4)
Run
-
-
5
-
35
50
mW
Idle “00” at M (0000)
-
-
5
-
12
18
mW
Minimum Data Retention Voltage, VDR
Data Retention Current, IDR
NOTES:
3. Typical values are for TA = +25oC and nominal VDD.
4. External clock: f = 5MHz, t R, t F = 10ns; CL = 50pF.
VDD = VDR
VDD = 2.4
-
2
2.4
V
-
25
100
µA
Dynamic Electrical Specifications at TA = -40o to +85oC; C L = 50pF; Input tR, tF = 10ns; Input Pulse Levels = 0.1V to
VDD -0.1V; VDD = 5V, ±5%.
CDP1805AC CDP1806AC
PARAMETER
(NOTE 5)
TYP
MAX
UNITS
Propagation Delay Times
Clock to TPA, TPB, tPLH, tPHL
Clock-to-Memory High-Address Byte, tPLH, tPHL
Clock-to-Memory Low-Address Byte, tPLH, tPHL
Clock to MRD, tPLH, tPHL
Clock to MWR, tPLH, tPHL (See Note 5)
Clock to (CPU DATA to BUS), tPLH, tPHL
Clock to State Code, tPLH, tPHL
Clock to Q, tPLH, tPHL
Clock to N, tPLH, tPHL
Clock to Internal RAM Data to BUS, tPLH, tPHL
150
275
ns
325
550
ns
275
450
ns
200
325
ns
150
275
ns
375
625
ns
225
400
ns
250
425
ns
250
425
ns
420
650
ns
5
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