CDP1878C View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

CDP1878C

CMOS Dual Counter-Timer

Intersil 

CDP1878C

Bit 3 - Gate Level Select - All modes require an enabling sig-

nal on the gate to allow counter operation. This enabling sig-

nal is either a level or a pulse (edge). Positive gate level or

edge enabling is selected by writing a “1” into this bit and

negative (low) enabling is selected when bit 3 is “0”.

Bit 4 - Interrupt Enable - Setting this bit to “1” enables the

INT output, and setting it to “0” disables it. When reset, the

INT output is at a high level. If the interrupt enable bit in the

control register is enabled and the counter decrements to

zero, the INT output will go low and will not return high until

the counter-timer is reset or the selected control register is

written to. Example: If timer B times out, control register B

must be accessed to reset the INT output high. If the inter-

rupt enable bit is set to “0”, the counter’s timeout will have no

effect on the lNT output.

In mode 5, the variable-duty cycle mode, the lNT pin will

become active low when the MSB in the counter has decre-

mented to zero.

Bit 5 - Start/Stop Control - This bit controls the clock input to

the counter and must be set to “1” to enable it. Writing a “0”

into this location will halt operation of the counter. Operation

will not resume until the bit is set to “1”.

Bit 6 - Holding Register Control - Since the counter may be

decrementing during a read cycle, writing a “1” into this loca-

tion will hold a stable value in the hold register for subse-

quent read operations. Rewriting a “1” into bit 6 will cause an

update in the holding register on the next trailing clock edge.

If this location contains a “0”, the holding register will be

updated continuously by the value in the counter.

Bit 7 - Jam Enable - When this bit is set to “1 “during a write

to the control register, the 16-bit value in the jam register will

be available to the counter; TAO and TBO are reset low and

TAO and TBO are set high. On the trailing edge of the first

input clock signal with the gate valid this value will be latched

in the counter, the counter outputs TAO and TBO will be set

high and the TAO and TBO will be reset low. Setting bit 7 to

“0” will leave the counter value unaffected. This location

should be set to “0” any time a write to the control register

must be performed without changing the present counter

value. If the value in the jam register has not been changed,

writing a “1” into bit 7 of the control register with zeros in bits

0,1, and 2 (mode select) will reload the counter with the old

value and leave the mode unchanged. If the value in the jam

register is changed, then the next write to the control register

(with bit 7 a “1”) must include a valid mode select (i.e., at

least 1 of the bits 0,1, or 2 must be a ”1”).

In mode 3, the hardware start is enabled by writing a “0” into

bit 7. If a “1” is written to bit 7, the timeout will start immedi-

ately and mode 3 will resemble mode 1.

Mode Descriptions

1

MODE

Timeout

CONTROL REGISTER

GATE CONTROL

XXXXX001

BUS 7

BUS 0

Selectable High or Low

Level Enables Operation

Mode 1

After the count is loaded into the jam register and the control

register is written to with the jam-enable bit high on the trail-

ing edge of the first clock after the gate is valid, TXO goes

high and TXO goes low. The input clock decrements the

counter as long as the gate remains valid. When it reaches

zero TXO goes low and TXO goes high, and if enabled, the

interrupt output is set low. Writing to the counter while it is

decrementing has no effect on the counter value unless the

control register is subsequently written to with the jam-

enable bit high. After timeout the counter remains at FFFF

unless reloaded.

COUNTER VALUE

CLOCK

WR CONTROL

REGISTER

5

4

3

2

1

1

0

5

4

3

2

1

1

0

STALL COUNTER

FFFF

GATE

TXO

INT

LOAD COUNT = 5

FIGURE 1. TIMEOUT (MODE 1) TIMING WAVEFORMS

4-96

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